A digital transmitter includes baseband interfaces to generate digital baseband signals with baseband frequencies, digital-upconverting stages to upconvert the baseband frequencies to first radio frequencies having a predetermined frequency range, a M-Band M modulator to modulate the up-stage signals based on noise shaping and noise quantization processes, delay registers to align phases of the modulated up-stage signals, a noise canceler to generate noise canceling signals with a converted polarity, a Switch Mode Power Amplifier to amplify the phase aligned modulated up-stage signals up to a predetermined power level, a linear power amplifier to amplify the noise canceling signals up to the predetermined power level, a power combiner to combine to generate transmitting signals by combining the amplified phase aligned modulated up-stage signals and the amplified noise canceling signals, and an antenna to transmit the transmitting signals.

An analog signals generating device comprises a current pump controlled by a control code generated by a module for calculating the digital code with shaping of noise. The calculation module receives as input a digital signal representative of the analog signal to be generated and comprises at least one quantizer and a quantization error compensating stage. The current pump comprises two groups of at least one electric current generator and two groups of at least one switching means, the switching facilities being controlled by the control signal and causing the electric currents to flow between the electric current generators and the inputs of a differential amplifier exhibiting a predominantly capacitive input impedance and connected in series between the two groups of switching means.

The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

A digital-to-analog converter (DAC) circuit includes a first DAC that produces a first analog output signal based upon a received multi-bit digital signal and upon a received clock. A second DAC that produces a second analog output signal based upon the received multi-bit digital signal and upon the received clock, wherein the first and second DACs are connected in parallel and process the same multi-bit digital signal. In one embodiment, the DACs produce differential signals. A low pass filter connected to receive the first and second analog outputs is configured to sum the first and second analog outputs and to filter the summed first and second analog outputs to produce an ingoing analog signal. An amplifier is connected to receive the ingoing analog signal to produce an amplified ingoing analog signal.

An audio amplifier system includes a delta-sigma modulator configured to receive an m-bit digital audio input signal and to generate a pulse density modulated signal based on the m-bit digital audio input signal. An analog power stage is coupled to the delta-sigma modulator to receive the pulse density modulated signal and amplify the pulse density modulated signal to generate an amplified pulse density modulated signal. A feedback circuit is coupled to the delta-sigma modulator and the analog power stage. The feedback circuit is configured to receive the amplified pulse density modulated signal and the pulse density modulated signal and to determine a digital error signal representative of a difference between the amplified pulse density modulated signal and the pulse density modulated signal. The feedback circuit is further configured to provide the digital error signal to the delta-sigma modulator for applying the digital error signal to a representation of the m-bit digital audio input signal.

Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

An audio digital-to-analog converter (DAC) achieves high dynamic range with low power consumption using a segmented DAC, also referred to as a noise shaped splitter. The noise shaped splitter is dynamically reconfigured based on envelope detection that tracks the amplitude of an n-bit digital input signal to the segmented DAC. The amplitude of the n-bit digital input signal can be expressed as the magnitude of a numerical value corresponding to the n bits of the digital signal. Based on the amplitude of the digital input signal, certain segments of the segmented DAC are bypassed and the components of each bypassed segment are turned off, saving power and reducing noise, and achieving improved dynamic range along with lower power consumption.

The purpose of the present invention is to provide a high-power-efficiency and low-design-cost transmission device by implementing, with a constant clock, delta-sigma modulation maintaining a zero current switching property in an amplifier. This delta-sigma modulator comprises: a pulse phase signal generation unit for generating a pulse phase signal from a phase signal; a delta-sigma modulation unit for generating a pulse amplitude signal obtained by delta-sigma modulating an amplitude signal with a constant clock; a phase sorting unit for outputting a control signal on the basis of the phase signal; a delay switching unit for delaying the pulse amplitude signal on the basis of the control signal; and a mixing unit for outputting a pulse string obtained by multiplying together the delayed pulse amplitude signal and the pulse phase signal.

The invention to mismatch and ISI shaping in a data converter. The invention provides a dynamic element matching technique that incorporates both mismatch and inter symbol interference shaping. A digital decoder is provided that controls the number of on and off transitions so that the resulting signal does not contain noise or distortion. The element selection technique of the invention is suitable for high resolution multi-bit continuous time oversampling data converters.