An RF transmitter module for a cellular radio that includes a delta-sigma modulator having a plurality of interleaving dynamic element matching (DEM) circuits providing interleaved digital bits at a reduced clock rate. An interleaver controller controls the DEM circuits so as to provide groups of the digital bits at different points in time. In one embodiment, a summation junction adds the groups of the digital bits to provide a continuous stream of the interleaved digital bits, a DAC converts the stream of interleaved digital bits to an analog signal, and a power amplifier amplifies the analog signal.

A semiconductor device such as a sigma delta A/D converter includes an integrator configured to output first and second output signals, a quantizer configured to generate a first digital signal based on the output signals, first and second switches configured to control application of first and second reference voltages to a first resistor based on respective first and second control signals, and a third switch configured to control connection between the first resistor and a first input terminal of the integrator based on a third control signal. The first through third control signals are generated based on the first digital signal and a second digital signal obtained by delaying the first digital signal. The third switch is turned on when any one of the first and second switches is turned on, and is turned off when both the first and second switches are turned off.

In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.

Fluxgate current transducer including a control circuit and a fluxgate measuring device comprising a fluxgate magnetic field detector, the fluxgate magnetic field detector comprising a saturable soft magnetic core surrounded by an excitation coil, the control circuit comprising an excitation coil drive circuit connected to the excitation coil and a controller connected to the excitation coil drive circuit configured to generate an alternating excitation current I.sub.fx to alternatingly saturate the soft magnetic core. The controller is in the form of a FPGA (Field Programmable Gate Array) comprising at least one input comprising a 1 bit sigma delta analog-to-digital converter (ADC) connected to the excitation coil to receive a measurement signal output by the excitation coil.

A charge analog-to-digital converter (ADC) for processing a signal from a micro electrical mechanical sensor (MEMS) sensor can include a pre-amplifier integrated into a feedback loop of a delta sigma modulator to provide a reduced power consumption configuration for processing of the signal from the MEMS sensor.