A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.

An apparatus is provided for channel encoding in a communication system using an LDPC code. The apparatus includes at least one processor configured to encode input bits using a Bose-Chaudhuri-Hocquenghem (BCH) code, shorten one or more bits of the encoded input bits according to a number of bit groups to be shortened and an order among a plurality of orders according to which the bit groups are shortened, wherein the number of bit groups to be shortened is based on a number of bits to be shortened which is based on a number of the encoded input bits, encode information bits including the encoded input bits and the shortened one or more bits, using an LDPC code to generate parity bits, and puncture one or more bits in the parity bits based on a puncturing parameter among puncturing parameters; and a transmitter configured to transmit a signal that is generated from the encoded information bits based on the punctured one or more bits. The plurality of orders are based on the puncturing parameters and include a first order and a second order that is different from the first order.

A base station may determine an SS block index associated with an SS block for transmission, and may scramble information based on at least a portion of the determined SS block index. The information may include at least one of a reference signal, data, paging information, control information, broadcast information, or a CRC associated with control information. The base station may transmit the SS block and scrambled information to a UE. A UE may receive an SS block and information scrambled based on at least a portion of an SS block index associated with the SS block. The information may include at least one of a reference signal, data, paging information, control information, broadcast information, or a CRC associated with control information. The UE may descramble the scrambled information based on the at least the portion of the SS block index.

In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.

In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.

The present disclosure discloses a system including a controller and a plurality of radio heads communicatively coupled to the controller. The controller transmits a synchronization signal to each of the radio heads to synchronize the local clocks in the radio heads to a master clock in the controller. The controller also transmits packets to the radio heads. Each of the radio heads includes a deframer. For a radio head, upon detecting that a received packet from the controller includes an error, the deframer alters the received packet to maintain the synchronization between the controller and the radio head and transmits data contained within the altered packet.

The present disclosure discloses a system including a controller and a plurality of radio heads communicatively coupled to the controller. The controller transmits a synchronization signal to each of the radio heads to synchronize the local clocks in the radio heads to a master clock in the controller. The controller also transmits packets to the radio heads. Each of the radio heads includes a deframer. For a radio head, upon detecting that a received packet from the controller includes an error, the deframer alters the received packet to maintain the synchronization between the controller and the radio head and transmits data contained within the altered packet.

A cyclic redundancy check, CRC, computation circuit comprising an input for receiving an input stream having an input bit sequence comprising two or more bits at a time aligned to rows of a CRC generator matrix stored in a Look Up Table, LUT; a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence; wherein the LUT comprises a plurality of addresses wherein at least one of the addresses is configured to store two or more rows of the CRC generator matrix; and the set of parallel processors is configured to: combine LUT data with the input stream by using two or more bits of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT; and combine generated two or more intermediate parity bit sequences into a single parity bit sequence.

Methods, systems, and devices for wireless communications are described. In some wireless communications system, a wireless device may append, during a first encoding stage, a first set of cyclic redundancy check bits having a first size to each code block of a plurality of code blocks and may concatenate two or more code blocks from the plurality of code blocks into a first set of code blocks, each code block of the two or more code blocks including the appended first set of cyclic redundancy check bits. The wireless device may further append, during a second encoding stage, a second set of cyclic redundancy check bits having a second size to the first set of code blocks, and may transmit a message comprising the plurality of code blocks including the appended first set of cyclic redundancy check bits and the appended second set of cyclic redundancy check bits.

A method and an optical sensor are described herein. The optical sensor may include a communication interface for receiving data from a control unit and for transmitting data to the control unit, a storage unit with at least one register for storing data, and a CRC generator for generating a CRC checksum. The optical sensor may be configured in such a way that when data stored in the storage unit is to be transmitted to the control unit, the communication interface receives from the control unit a device address specific to the optical sensor and an address of a register in which the data to be transmitted is stored. The CRC generator may be initialized using the device address received from the communication interface and/or the register address received from the communication interface, before the CRC generator generates a CRC checksum for the data to be transmitted.