H03M13/09

ELECTRONIC DEVICE HAVING A CRC GENERATOR AND METHOD FOR TRANSMITTING DATA FROM AN ELECTRONIC DEVICE TO A CONTROL UNIT
20220353013 · 2022-11-03 ·

A method and an optical sensor are described herein. The optical sensor may include a communication interface for receiving data from a control unit and for transmitting data to the control unit, a storage unit with at least one register for storing data, and a CRC generator for generating a CRC checksum. The optical sensor may be configured in such a way that when data stored in the storage unit is to be transmitted to the control unit, the communication interface receives from the control unit a device address specific to the optical sensor and an address of a register in which the data to be transmitted is stored. The CRC generator may be initialized using the device address received from the communication interface and/or the register address received from the communication interface, before the CRC generator generates a CRC checksum for the data to be transmitted.

METHOD AND SYSTEM FOR UPDATING A MEDICAL DEVICE
20230092591 · 2023-03-23 ·

The present disclosure includes methods, devices and systems for establishing a connection between a medical device and a remote computing device, receiving an upgrade command at the medical device, storing a current version of persistent data and a current version of executable code in a first storage area of the medical device, transmitting at least the current version of the persistent data to the remote computing device, receiving a second format of the current version of the persistent data and an upgraded version of executable code at the medical device, storing the second format of the current version of the persistent data and the upgraded version of the executable code in a second storage area of the medical device, and executing the upgraded version of the executable code with the second format of the current version of the persistent data.

METHOD AND SYSTEM FOR UPDATING A MEDICAL DEVICE
20230092591 · 2023-03-23 ·

The present disclosure includes methods, devices and systems for establishing a connection between a medical device and a remote computing device, receiving an upgrade command at the medical device, storing a current version of persistent data and a current version of executable code in a first storage area of the medical device, transmitting at least the current version of the persistent data to the remote computing device, receiving a second format of the current version of the persistent data and an upgraded version of executable code at the medical device, storing the second format of the current version of the persistent data and the upgraded version of the executable code in a second storage area of the medical device, and executing the upgraded version of the executable code with the second format of the current version of the persistent data.

CYCLIC REDUNDANCY CHECK, CRC,DECODING USING THE INVERSE CRC GENERATOR POLYNOMIAL
20220352901 · 2022-11-03 · ·

A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(−K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.

Fast CRC computation circuit using an on-the-fly reconfigurable generator polynomial
11489544 · 2022-11-01 · ·

A circuit for generating an N-bit cyclic redundancy code of a k-bit digit d, the code based on a reconfigurable generator polynomial P of degree N, the circuit including a dynamic table comprising a multiplication sub-table storing products resulting from multiplication by the polynomial P of each element definable over k bits, in the order of the scalar values of the k-bit elements; a division sub-table storing quotients resulting from Euclidean division by the polynomial P of each k-bit element shifted by N bits to the left, in the order of the scalar values of the k-bit elements; and a group of first multiplexers, each multiplexer connected to be indexed by a respective cell of the division table to transmit the contents of a corresponding cell of the multiplication table to an output of the dynamic table, of same rank as the respective cell of the division table.

Utilizing Integrity Information to Determine Corruption in a Vast Storage System

A method includes determining a plurality of identifiers based on a data retrieval request. Integrity information is generated based on determining the plurality of identifiers. Stored integrity information corresponding to the data retrieval request is compared with the integrity information. When the stored integrity information compares unfavorably with the integrity information, corruption associated with the plurality of identifiers is determined.

ERROR DETECTION IN MEMORY SYSTEM

A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.

ERROR DETECTION IN MEMORY SYSTEM

A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.

SINGLE-CYCLE BYTE CORRECTING AND MULTI-BYTE DETECTING ERROR CODE

A memory device and a system that implements a single symbol correction, double symbol detection (SSC-DSD+) error correction scheme are provided. The scheme is implemented by calculating four syndrome symbols in accordance with a Reed-Solomon (RS) codeword; determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols; and generating an output based on a comparison of the three location bytes. The output may include: corrected data responsive to determining that the three location bytes match; an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match. A variant of the SSC-DSD+ decoder may be implemented using a carry-free subtraction operation to perform sanity checking.

ACCESSORY, METHOD OF CONTROLLING ACCESSORY, ELECTRONIC DEVICE, METHOD OF CONTROLLING ELECTRONIC DEVICE, COMMUNICATION SYSTEM, AND STORAGE MEDIUM
20220345156 · 2022-10-27 ·

An accessory and an electronic device enabling retransmission of data from the electronic device to the accessory when a checksum error occurs in the accessory. An accessory controller of the accessory determines whether or not a checksum received from the camera and a first checksum calculated from data received from the camera match. In a case where the checksums match, the accessory controller calculates a second checksum, whereas in a case where the checksums do not match, the accessory controller calculates a third checksum. The accessory controller transmits the second checksum or the third checksum to the camera according to a result of the determination.