A method of producing a set of coded bits from a set of information bits for transmission between a first node and a second node in a wireless communications system, the method comprises generating a codeword vector by encoding the set of information bits with a low-density parity-check code, wherein the codeword vector is composed of systematic bits and parity bits. The method comprises performing circular buffer-based rate matching on the generated codeword vector to produce the coded bits for transmission, wherein the circular buffer-based rate matching comprises puncturing a first plurality of systematic bits.

This application provides a data transmission method, a base station, and a terminal device. The method includes: determining, by a base station, a target base graph in N Raptor-like LDPC base graphs; and sending, by the base station, indication information to a terminal device, where the indication information is used to indicate the terminal device to use the target base graph to perform LDPC encoding and decoding. Based on the foregoing technical solution, the base station may determine a target base graph in a plurality of Raptor-like LDPC base graphs that may be used to perform LDPC encoding and decoding, and indicate the target base graph to the terminal device. Further, for one code rate or one code length, the base station may select different base graphs as required.

Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate message probability compute data based on encoded data (e.g., data encoded using one or more encoding techniques). The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate message probability compute data for a message probability compute (MPC) decoder. In this manner, neural networks or recurrent neural networks described herein may be used to implement aspects of error correction coding (ECC) decoders, e.g., an MPC decoder that iteratively decodes encoded data.

Embodiments provide an interleaver for interleaving an LDPC encoded bit sequence, wherein the interleaver includes a segmentation stage configured to segment the LDPC encoded bit sequence into a plurality of chunks including a first chunk and one or more other chunks, a first interleaver stage, configured to interleave the one or more other chunks or a concatenated version thereof, a second interleaver stage, configured to block wise interleave the first chunk and an interleaved bit sequence provided by the first interleaver stage, to obtain an interleaved version of the LDPC encoded bit sequence, wherein the first chunk consists of bits of a first type being, which are error correcting bits or repeat accumulate bits of the LDPC encoded bit sequence, or are represented, in a Tanner graph representation of the LDPC encoded bit sequence, by variable nodes that include non-random connections to at least two error correcting check nodes.

A memory includes a first check matrix calculation circuit suitable for generating a first parity by calculating a group indicator portion of a check matrix and a write data; a memory core suitable for storing the write data and the first parity; a first syndrome calculation circuit suitable for generating a first syndrome by adding the first parity which is read from the memory core to a first calculation result obtained by calculating the group indicator portion and the data which is read from the memory core; and a failure determination circuit suitable for accumulating the first syndromes for a region of the memory core to generate a vector and determining a presence of a failure of the region based on the vector.

A chip includes a dedicated scheduler, a general scheduler, and a plurality of hardware accelerators. The hardware accelerators are connected, at least one hardware accelerator is connected to the dedicated scheduler, and at least one hardware accelerator is connected to the general scheduler.

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

The present invention provides an apparatus of transmitting broadcast signals. The apparatus includes, an encoder for encoding service data, a bit interleaver for bit interleaving the encoded service data, a mapper for mapping the bit interleaved service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, an OFDM modulator for modulating data in the built at least one signal frame by an OFDM scheme and a transmitter for transmitting the broadcast signals having the modulated data.

One coding method of a plurality of coding methods including at least a first coding method and a second coding method is selected, an information sequence is encoded by using the selected coding method, and an encoded sequence obtained by performing predetermined processing on the information sequence is modulated and transmitted. The first coding method is a coding method having a first coding rate, for generating a first encoded sequence by performing puncturing processing on a generated first codeword by using a first parity check matrix. The second coding method is a coding method having a second coding rate, for generating a second encoded sequence by performing puncturing processing on a generated second codeword by using a second parity check matrix that is different from the first parity check matrix, the second coding rate after the puncturing process being different from the first coding rate.