An information processing apparatus includes: a decoding module, configured to receive M first codewords from at least one peer device, where each first codeword includes first service data with a K-unit length and an error correction code with an R-unit length, where the decoding module is further configured to decode the M first codewords to obtain M second codewords, where a length of each second codeword is a sum of the K-unit length and the R-unit length, each second codeword includes second service data with the K-unit length and error correction information, the second service data is error-corrected first service data; and a classification and statistics collection module, configured to determine a bit error rate of the first service data based on the error correction information.

An information processing apparatus includes: a decoding module, configured to receive M first codewords from at least one peer device, where each first codeword includes first service data with a K-unit length and an error correction code with an R-unit length, where the decoding module is further configured to decode the M first codewords to obtain M second codewords, where a length of each second codeword is a sum of the K-unit length and the R-unit length, each second codeword includes second service data with the K-unit length and error correction information, the second service data is error-corrected first service data; and a classification and statistics collection module, configured to determine a bit error rate of the first service data based on the error correction information.

A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.

Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.

An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

A method for extending a polar code by determining an extension number E such that E/2<N<E whereby N is a number of codeword bits for a polar code that is to be extended and extending a codeword by adding additional redundant/extension bits. Information indicative of a bit unreliability associated with each bit in the codeword is accessed and bit positions with the highest unreliabilities are selected. Input data for an extended codeword is determined by adding a number of redundant bits in the respective selected bit positions.

A method for extending a polar code by determining an extension number E such that E/2<N<E whereby N is a number of codeword bits for a polar code that is to be extended and extending a codeword by adding additional redundant/extension bits. Information indicative of a bit unreliability associated with each bit in the codeword is accessed and bit positions with the highest unreliabilities are selected. Input data for an extended codeword is determined by adding a number of redundant bits in the respective selected bit positions.