The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an example, the second matrix may be decomposed into a lower triangular matrix and an upper triangular matrix, and the parity check symbols may be computed by performing a forward substitution and a backward substitution using the lower and upper triangular matrices. The Reed-Solomon encoder circuit may generate a Reed-Solomon code word by combining the data symbols and the parity check symbols, and provide the Reed-Solomon code word at an output port.

A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data.

Certain aspects of the present disclosure generally relate to techniques for encoding and decoding bits of information using cyclic redundancy check (CRC) concatenated polar encoding and decoding. The CRC concatenated polar encoding techniques may avoid transmission of dummy bits. A method generally includes obtaining the bits of information to be transmitted. The method includes performing CRC outer encoding of the bits of information using an even-weighted generator polynomial to produce CRC encoded bits. The method includes performing polar inner encoding of the CRC encoded bits to generate a codeword. The method includes discarding a first code bit at a beginning of the codeword. The shortened codeword is transmitted over a wireless medium. In another method, bit-level scrambling is performed on the CRC encoded bits before the polar encoding to avoid generating a dummy bit. In another method, only odd-weighted generator polynomials are selected to avoid generating the dummy bit.

The present invention is directed to data communication systems and methods thereof According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

Certain aspects of the present disclosure generally relate to techniques for encoding and decoding bits of information using cyclic redundancy check (CRC) concatenated polar encoding and decoding. The CRC concatenated polar encoding techniques may avoid transmission of dummy bits. A method generally includes obtaining the bits of information to be transmitted. The method includes performing CRC outer encoding of the bits of information using an even-weighted generator polynomial to produce CRC encoded bits. The method includes performing polar inner encoding of the CRC encoded bits to generate a codeword. The method includes discarding a first code bit at a beginning of the codeword. The shortened codeword is transmitted over a wireless medium. In another method, bit-level scrambling is performed on the CRC encoded bits before the polar encoding to avoid generating a dummy bit. In another method, only odd-weighted generator polynomials are selected to avoid generating the dummy bit.

Certain aspects of the present disclosure generally relate to techniques for encoding and decoding bits of information using cyclic redundancy check (CRC) concatenated polar encoding and decoding. A method generally includes obtaining the bits of information to be transmitted. The method includes performing CRC outer encoding of the bits of information using an even-weighted generator polynomial to produce CRC encoded bits. The method includes performing polar inner encoding of the CRC encoded bits to generate a codeword. The method includes discarding a first code bit at a beginning of the codeword. The shortened codeword is transmitted over a wireless medium. In another method, bit-level scrambling is performed on the CRC encoded bits before the polar encoding to. In another method, only odd-weighted generator polynomials are selected.

Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.

The present disclosure relates to a decoding method. The decoding method includes a sequentially determining series of source bits from a codeword by performing a first decoding operation and a second decoding operation. For instance, a series of N source bits may be divided into a first bit group of X source bits and a second bit group of Y source bits. The initial X source bits are sequentially determined in the first decoding operation and the remaining Y source bits are sequentially determined in the second decoding operation. The first decoding operation includes sorting at least 2L reliability values, which are calculated from L bit sequences, where L is an integer greater than 0. The second decoding operation includes determining a source bit in each of the L bit sequences, based on the at least 2L reliability values.

A signal processor including a Pulse Width Modulation (PWM) encoder configured to encode data into a data PWM pattern; and a block encoder coupled to the PWM encoder, and configured to determine a checksum of the data PWM pattern, wherein the PWM encoder is further configured to encode the checksum into a checksum PWM pattern, and append the checksum PWM pattern on the data PWM pattern for transmission as a PWM signal.