Methods and systems for encoding data are described herein. The method comprises inputting data to a first pipeline of a non-systematic polar encoder capable of encoding a polar code of length n.sub.max, extracting, via at least one first multiplexer of size log n.sub.max1, a first polar code of length n<n.sub.max at a first location along the first pipeline to generate a first encoded output, modifying the first encoded output to set frozen bits to a known value to obtain a modified first encoded output, inputting the modified first encoded output to a second pipeline of the non-systematic polar encoder, and extracting, via at least one second multiplexer of size log n.sub.max1, a second polar code of length n<n.sub.max at a second location along the second pipeline to generate a second encoded output, the second encoded output corresponding to a systematically encoded polar code of length n.

The disclosure provides a very flexible mechanism for a storage controller to create RAID stripes and to re-create corrupted stripes when necessary using the erasure coding scheme. Typically, this is known as a RAID 6 implementation/feature. The erasure code calculations are generated using the Galois Multiplication hardware and the system controller can pass any polynomial into the hardware on a per stripe calculation basis. The polynomial value is passed to the hardware via an input descriptor field. The descriptor controls the entire computation process.

Methods and apparatus for operating a communication system comprising three or more communication transceivers. In illustrative embodiments, multiple different cyclic redundancy check (CRC) generation schemes are maintained. Each CRC generation scheme corresponds to a unique CRC residual value. A CRC value generated using one of the CRC generation schemes is placed in a data packet to be transmitted. The chosen CRC generation scheme reflects which one or more transceivers are intended recipients of the data packet. When a data packet is received by a transceiver, a CRC residual value is calculated based on the CRC value contained in the received data packet. The calculated CRC residual value is compared against a list of one or more valid CRC residual values for that particular transceiver. If the calculated CRC value matches one of the listed valid CRC residual values, the data packet is accepted, otherwise it is rejected.

A construction method for a (n,n(n1),n1) permutation group code based on coset partition is provided. The presented (n,n(n1),n1) permutation group code has an error-correcting capability of d1 and features a strong anti-interference capability for channel interferences comprising multi-frequency interferences and signal fading. As n is a prime, for a permutation code family with a minimum distance of n1 and a code set size of n(n1), the invention provides a method of calculating n1 orbit leader permutation codewords by O.sub.n={o.sub.1}.sub.=1.sup.n-1(mod n) and enumerating residual codewords of the code set by P.sub.n=C.sub.nO.sub.n={(l.sub.1).sup.n-1O.sub.n}={(r.sub.n).sup.n-1O.sub.n}. Besides, a generator of the code set thereof is provided. The (n,n(n1),n1) permutation group code of the invention is an algebraic-structured code, n1 codewords of the orbit leader array can be obtained simply by adder and (mod n) calculator rather than multiplication of positive integers. Composition operations of the cyclic subgroup C.sub.n acting on all permutations o.sub. of the orbit leader permutation array O.sub.n are replaced by well-defined cyclic shift composite operation functions (l.sub.1).sup.n-1 and (r.sub.n).sup.n-1 so that the action of the cyclic group acting on permutations is realized by a group of cyclic shift registers.

A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to 0 and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a determined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the determined column among one or more column(s) of the parity check matrix.

A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to 0 and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a determined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the determined column among one or more column(s) of the parity check matrix.

In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

Technology that detects computation errors is disclosed, in which a system may include one or more processors and storage logic. The storage logic may be executed by the one or more processors to perform operations comprising: receiving a data vector, the data vector including a plurality of ordered blocks; transposing the data vector into a set of sub vectors, each of the sub vectors including a corresponding data element from each of the ordered blocks; generating a set of discrete cyclic redundancy checks (CRCs) based on the set of sub vectors; transposing the set of discrete CRCs into a set of mixed CRCs, each of the mixed CRCs including a CRC data element from each of the discrete CRCs; and compacting the set of mixed CRCs into a reduced CRC.

The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.