Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.

Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

A spread-spectrum-signal reception apparatus includes a controller to obtain a phase comparison value that is a phase of a spread code at a time at which initialization of a phase of the spread code is performed and which corresponds to a timing of a top of a frame of a received signal, and to output an initialization instruction including the phase comparison value when having determined that a current time is within a range of a time window; and a signal processor to demodulate the received signal in accordance with the spread code, to perform a frame synchronizing process on the demodulated signal to detect a frame timing, and to perform the initialization at a timing determined in accordance with a result of comparison between the phase comparison value included in the initialization instruction and a phase of the spread code at the frame timing.

An apparatus is provided which comprises: a first circuitry to track a spread spectrum of a differential signal according to sampled data; and a second circuitry to adjust phase of a clock according to the spread spectrum, wherein the clock is used for sampling the differential signal.

The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.

Communication system, comprising: a first data bus configured to transport a first data signal according to a first transmission direction; a second data bus configured to transport a second data signal according to a second transmission direction different from the first transmission direction; a synchronization bus; and a plurality of local resources generating a respective local signal to be transmitted on the first and second data bus. All transceivers are modulated with CDMA encoding and take place following a synchronism signal. The unidirectionality of transmission on the data buses guarantees the absence of interference. The communication system is fully scalable.

A candidate arbitrary-phase spread spectrum modulation technique that offers similar performance to spread continuous phase modulation (CPM) waveforms and additional capabilities for programming a chosen frequency domain spectra into the resulting spread spectrum signal. The proposed chaotic-FSK waveform is derived from high-order sequence-based spread spectrum signals, with multi-bit resolution chaos-based sequences defining incremental phase words, enabling real-time efficient generation of practically non-repeating waveforms. A result of the C-FSK formulation is a parameterized hybrid modulation capable of acting like a traditional sequence-based spread spectrum signal or a traditional frequency shift keying signal depending on chosen parameters. As such, adaptation in this modulation may be easily implemented as a time-varying evolution, increasing the security of the waveform while retaining many efficiently implementable receiver design characteristics of traditional PSK modulations.

A clock and data recovery module includes a clock and data recovery loop and a spread spectrum clock tracking circuit. The clock and data recovery loop includes a clock and data recovery unit and a first phase interpolator. The first phase interpolator is coupled to the clock and data recovery unit and configured to generate a data clock signal and an edge clock signal according to a phase signal and a reference clock signal. The clock and data recovery unit is configured to generate the phase signal according to a data signal, the data clock signal and the edge clock signal. The spread spectrum clock tracking circuit is configured to generate the reference clock signal according to the data signal, and to transmit the reference clock signal to the first phase interpolator. The spread spectrum clock tracking circuit is decoupled to the clock and data recovery loop.

Provided is a technique that can generate a spread spectrum clock signal in all of an upper-spread mode, a down-spread mode, and a center-spread mode. A spread spectrum clock generator (2) spreads a spectrum of a signal with a predetermined carrier frequency to generate a spread spectrum clock signal under the control of a control unit (13). The control unit includes carrier frequency correction control means (13b). The carrier frequency correction control means shifts the predetermined carrier frequency to generate, from one spread mode, a spread spectrum clock signal of another pseudo spread mode.

A method and a device are described for determining data from a signal spread over at least one frequency base band representing the data. The method for generating a signal has a step of using at least one highly auto-correlated spread code sequence (1C, 2C) associated with the frequency base band for determining a delay with which a modulated portion (1P, 2P) of the data is spread on the signal. The method has further steps of determining said modulated portion from the signal using the delay and the spread code sequence (1C, 2C), of demodulating the modulated portion (1P, 2P) using phase shift keying, and of determining a remainder (1R, 2R) of the data using the delay.