Patent classifications
H04J3/0635
Display method and display apparatus
A display method is for a display apparatus to display an image, and includes: obtaining a captured display image and a decode target image by an image sensor capturing an image of a subject; obtaining a light ID by decoding the decode target image; transmitting the light ID to a server; obtaining, from the server, an AR image and recognition information which are associated with the light ID; recognizing a region according to the recognition information as a target region from the captured display image; and displaying the captured display image in which the AR image is superimposed on the target region.
Systems and methods for indicating when frames egress a PHY module of a network device
A network device is provided and includes a physical layer module and a control port. The physical layer module includes one or more ports, which: receives and alters a first synchronization frame to include a timestamp indicating a received time. The control port: receives the first synchronization frame from the one or more ports; provides the first synchronization frame to a control module; and receives, from the control module a second synchronization frame including the timestamp and a follow up frame corresponding to the second synchronization frame. The one or more ports: receives the second synchronization and follow up frames from the control port and transmits the received frames from the network device; and generates an egress timestamp for the second synchronization frame and updates a timestamp field of the follow up frame or calculates a residence time and updates a correction field of the follow up frame.
Directed acyclic graph optimization based on timing information for generating optimized network clock
In one embodiment, a method comprises receiving, by a network device, one or more advertisement messages comprising timing information describing a quality of a network clock that is originated by a master clock device at a root of a directed acyclic graph (DAG); the network device executing an objective function for the DAG providing an optimized loopless time topology for the network clock, synchronized to the master clock device, based on the timing information; and the network device attaching to a parent device in the DAG based on the objective function, for optimized generation of the network clock by the network device.
SHAPING OF POST-SCHEDULING NETWORK PIPELINE JITTER
Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.
Low-latency metadata-based packet rewriter
Provided are systems, methods, and integrated circuits for a low-latency, metadata-based packet rewriter. In various implementations, an integrated circuit may include a first pipeline stage operable to receive packet bytes for a packet and packet information. The first stage may further be operable to extract a first value from the packet bytes, and provide the packet bytes, packet information, and first value. The integrated circuit may further include a second stage, operable to receive the packet bytes and packet information. The second stage may further calculate a value using a value from the packet information, and provide the packet bytes, packet information, and second value. The integrated circuit may further include a third stage, operable to receive the packet bytes, packet information, and a third value. The third stage may further be operable to insert the third value into the packet bytes, and provide the packet bytes and packet information.
SYSTEMS AND METHODS FOR CLOCK SYNCHRONIZATION
The present disclosure relates to a device and methods for clock synchronization. The device may include a first synchronization component and one or more second synchronization components. The first synchronization component may be configured to transmit a first synchronization signal to the one or more second synchronization components. Each second synchronization component of the one or more second synchronization components may be configured to generate a second synchronization signal based on the first synchronization signal and transmit the second synchronization signal to one or more detectors. The second synchronization signal may be configured to reset a clock of a detector of the one or more detectors corresponding to the each second synchronization component.
Content synchronization using micro-seeking
Methods and systems are disclosed maintaining playback of content at a target or desired playback time. A playback device may be configured to compare a current playback time of a content asset to a target playback time of the content asset and to determine, for each comparison, whether a difference between the current playback time and the target playback time has reached a threshold. Based on determining that the difference between the current playback time and the target playback time has reached a threshold, the playback device may seek to the target playback time of the content asset. The playback device may be configured to repeatedly perform the comparing, determining and seeking operations in order to maintain the current playback time of the content within the threshold of the target playback time.
Synchronization mechanism for high speed sensor interface
A sensor may determine, based on two or more synchronization signals provided by a control device, an expected time for receiving an upcoming synchronization signal. The sensor may perform a measurement of a sensor signal at a point in time such that sensor data, corresponding to the measurement of the sensor signal at the point in time, is available at a selectable time interval prior to reception of the upcoming synchronization signal.
TIME-SYNCHRONIZING A GROUP OF NODES
Systems and methods include receiving, values of one or more first external time variables from a first external node and values of one or more second external time variables from a second external node. The values of one or more local time variables of the local node are adjusted based at least upon the values of the one or more first external time variables and the values of the one or more second external time variables.
Use of orthogonal or near orthogonal codes in reverse link
An apparatus and method for use with a shared access communication channel is disclosed. A wireless network device receives signals and recovers data from a first plurality of subscriber units and a second plurality of subscriber units in a time interval. Received signals from the first plurality of subscriber units are distinguishable by having unique pseudo noise (PN) sequence with respect to others of the first plurality of subscriber units. Received signals the second plurality of subscriber units are distinguishable by a unique orthogonal sequence with respect to others of the second plurality of subscriber units. Received signals are distinguished between the first and second plurality of subscriber units based on detection of an orthogonal sequence present only in the received signals from the second plurality of subscriber units.