An apparatus for time aware audio streams is described herein. The apparatus includes a converter and an alignment unit. The converter is to perform sample rate conversion of data from a first clock to a second clock. The alignment unit is to indicate valid sample points in the data based on a relationship between the first clock and the second clock.

A method includes receiving an optical signal through an optical link and determining a receiving power for the optical link. The method further includes comparing the receiving power for the optical link to a first receiving power threshold and transitioning a clock and data recovery circuit form a normal mode to a holdover mode when the receiving power is less than the first receiving power threshold. The clock and data recovery circuit, when operating in the holdover mode, configured to hold a recovered clock to a known-good clock frequency. When the receiving power for the optical link is greater than a second receiving power threshold, the method initiates a transition of the clock and data recovery circuit from the holdover mode to the normal mode and reacquires synchronization between the recovered clock and a current rate of the incoming data stream using the known-good clock frequency.

A clock synchronization packet exchanging method includes sending, by a first device in a Flexible Ethernet (FlexE) group, a first FlexE instance at a first physical layer (PHY), where the first FlexE instance includes a clock synchronization packet, and a second FlexE instance sent by the first device in the FlexE group at a second PHY also includes a clock synchronization packet. The clock synchronization packets are carried in a plurality of FlexE instances transmitted between a transmit end and a receive end in the FlexE group.

A method and structure for equalization in coherent optical receivers. Block-based LMS (BLMS) algorithm is one of the many efficient adaptive equalization algorithms used to (i) increase convergence speed and (ii) reduce implementation complexity. Since the computation of the equalizer output and the gradient of the error are obtained using a linear convolution, BLMS can be efficiently implemented in the frequency domain with the constrained frequency-domain BLMS (FBLMS) adaptive algorithm. The present invention introduces a novel reduced complexity constrained FBLMS algorithm. This new approach replaces the two discrete Fourier transform (DFT) stages required to evaluate the DFT of the gradient error, by a simple frequency domain filtering. Implementation complexity can be drastically reduced in comparison to the standard constrained FBLMS. Furthermore, the new approach achieves better performance than that obtained with the unconstrained FBLMS in ultra-high speed coherent optical receivers.

Embodiments of this application provide a clock phase recovery apparatus and method, and a chip. The clock phase recovery apparatus includes an ADC, a dispersion compensation unit, a digital interpolator, a MIMO equalization unit, and a clock offset phase obtaining unit. The ADC is connected to the dispersion compensation unit, and the dispersion compensation unit is connected to a first input end of the digital interpolator. An output end of the digital interpolator is connected to an input end of the MIMO equalization unit, and an output end of the MIMO equalization unit is connected to an input end of the clock offset phase obtaining unit. The digital interpolator is configured to adjust, based on first offset phase information output by the clock offset phase obtaining unit, a dispersion-compensated signal output by the dispersion compensation unit.

A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.

Control apparatus to control operation of a data buffer to which data items are written according to a write pointer which advances in position in response to an input data item rate and from which data items are read according to a read pointer which advances in position in response to an output data item rate, comprises: a detector configured to detect an occupancy difference between a current buffer occupancy and a target buffer occupancy, in which the current buffer occupancy represents a difference between the read and write pointers; an output data item interpolator configured to interpolate a data item at an interpolated data buffer location displaced by a read offset displacement from a data buffer location pointed to by the read pointer; and output control circuitry configured, in response to a current occupancy difference exceeding a threshold occupancy difference, to change the read pointer from an initial read pointer to a target read pointer by a change amount so as to reduce the occupancy difference, the output control circuitry being configured to progressively vary the read offset displacement so as to define an interpolated data buffer location which progresses over the output of a transitional group of data items towards the location pointed to by the target read pointer; the output control circuitry being further configured, when the occupancy difference is less than the threshold occupancy difference and the interpolated data buffer location is aligned with the target read pointer, to inhibit operation of the output data item interpolator and to control output of an output data item from the data buffer location pointed to by the read pointer.

Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.