Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A sensor may determine a sampling pattern based on a group of synchronization signals received by the sensor. The sampling pattern may identify an expected time for receiving an upcoming synchronization signal. The sensor may trigger, based on the sampling pattern, a performance of a sensor operation associated with the upcoming synchronization signal. The performance of the sensor operation may be triggered before the upcoming synchronization signal is received.

A data recovery circuit adjusts skew between a first and second clock signals when a signal level of recovered data changes relative to first reference level between a first timing of the first clock signal and a second timing of the second clock signal. Prior to adjusting the skew, a first signal level of the recovered data at the first timing is compared to a second and/or a third reference level. A second signal level at the second timing is compared to the second and/or the third reference level. The skew is adjusted based on a first sign of an error of the first signal level relative to one of the second and third reference levels. The first sign is opposite to a second sign of an error of the second signal level relative to another one of the second and third reference levels.

A clock and data recovery device includes an extraction circuit and a phase detection circuit. The extraction circuit extracts transition information including data information corresponding to a value of data and edge information corresponding to transition of the value of the data, from a multivalued input data signal subjected to pulse amplitude modulation in synchronization with a clock from an oscillator. The phase detection circuit uses transition information selected based on a predetermined condition, when executing a phase error determination of the clock with respect to the input data signal based on the transition information extracted by the extraction circuit.

The present invention is designed so that data can be decoded suitably even when multiple transmission time interval lengths are used in one carrier. According to one aspect of the present invention, a user terminal has a receiving section that receives a DL signal in a second transmission time interval (TTI) having a longer TTI length than a first TTI, and a control section that saves soft bits of the received DL signal, and controls a decoding process using the saved soft bits and a retransmitted DL signal, and, when a DL signal that is transmitted in the first TTI is scheduled in a resource allocated to the DL signal transmitted in the second TTI, the control section controls the decoding process without using a soft bit corresponding to the DL signal that is transmitted in the first TTI.

A sensor may determine a sampling pattern based on a group of synchronization signals received by the sensor. The sampling pattern may identify an expected time for receiving an upcoming synchronization signal. The sensor may trigger, based on the sampling pattern, a performance of a sensor operation associated with the upcoming synchronization signal. The performance of the sensor operation may be triggered before the upcoming synchronization signal is received.

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.

Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, where the symbols are transmitted at a particular frequency with each of the symbols occurring over a unit interval (UI) time period. The first clock signal is input to a flip-flop logic included in a delay loop, and serves to trigger the first flip-flop logic. A second clock signal is generated using a programmable generator in the delay loop and has a frequency of a half UI and is fed back to a data input of the flip-flop. The output of the flip-flop is used as a recovered clock signal for the CDR at a half rate frequency. This design provides ease of timing control, a delay line without extra nonlinear-effects, and less hardware overhead.