Embodiments of the present disclosure utilizes the natural properties of RFI noise on a wireline link. Since differential RFI noise in the system has some correlation with the common mode noise on the cable, a replica of RFI noise can be regenerated by an adaptive filter based on information about the common mode noise. The replica RFI is subtracted from the equalizer output prior to the data decision circuitry or slicer. In this method, the system does not require expensive cable, nor does the equalizer suffer additional loss due to an RFI notch filter. Since RFI can be detected and mitigated, this information can also be coupled to safety systems to increase functional safety under high EMI conditions.

An input stage for an LVDS receiver circuit is provided, which includes at least one supply voltage connection as well as a first and a second stage input to be acted upon by a differential input signal pair. The input stage further includes a first and a second differential stage, the stage inputs being directly connected to one input each of the first differential stage and indirectly, via one level-shifting circuit each, to one input each of the second differential stage. According to the present invention, the first and the second differential stage are connected to the supply voltage connection via one transistor each of a third differential stage, the control input of one of these transistors being connected to a measuring path connecting the stage inputs to one another, with the control input of the other transistor being connected to an apparatus/device (arrangement) for providing a reference voltage.

A signal transmission device is provided, including a plurality of positive differential pins, a plurality of negative differential pins, a plurality of ground pins, a plurality of power signal pins, and a plurality of control signal pins. A first positive differential pin of the plurality of positive differential pins transmits a positive signal content of a first differential signal. A second positive differential pin transmits a positive signal content of a second differential signal. A first negative differential pin of the plurality of negative differential pins transmits a negative signal content of the first differential signal. A second negative differential pin transmits a negative signal content of the second differential signal. The first positive differential pin and the first negative differential pin are located on one side of a first ground pin, and the second positive differential pin and the second negative differential pin are located on the other side.

The present application discloses a method for storing data of a transmission signal, which includes: upon the reception of the transmission signal, analyzing a clock signal corresponding to the transmission signal to obtain a signal frequency of the clock signal; according to the signal frequency, acquiring zero-volt time points of a clock signal after signal superposition with the transmission signal; acquiring a preset time length, and according to the zero-volt time points and the preset time length, generating data storage time periods with each of the zero-volt time points as a central time point; and storing data of the transmission signal within each of the data storage time periods. The present application further provides an apparatus for storing data of a transmission signal and a computer readable storage medium.

Apparatus for communicating across an isolation barrier. In one embodiment, the apparatus comprises a transformer having a first winding disposed on a first side of a printed circuit board (PCB) and coupled to a first local ground, and a second winding disposed on a second side of the PCB, the second side opposite to the first side, and coupled to a second local ground; a transmitter coupled to the first winding; and a receiver, coupled the second winding, that generates an output signal based on a signal received from the transmitter.

According to one embodiment, in a first state, a control circuit determines, based on first information and second information, information on a request that includes a setting of a transmission circuit of a host to be set as an initial setting in a second state. The first state is a state of communicating with a host at a first communication speed conforming to a first specification. The second state is a state of communicating with the host at a second communication speed conforming to a second specification. The second communication speed is different from the first communication speed. The first information is information on a request of a setting of the transmission circuit of the host. The second information is information on a quality of a signal received by a reception circuit, which has been transmitted from the transmission circuit of the host.

A detector circuit for galvanically isolated transmission of digital signals. The detector circuit includes two differential signal inputs, one input common-mode voltage connection, one alternating voltage coupling, and one differential stage. The detector circuit also includes one operating voltage connection, one operating ground connection, one signal output, one bias current connection, and one rectifier stage. The alternating current coupling includes two capacitors and two resistors. The differential stage includes a first n-channel transistor and a second n-channel transistor. The bias current connection is connected to the differential stage via a third n-channel transistor. The bias current connection is connected to the rectifier stage via a fourth n-channel transistor and a fifth n-channel transistor. The rectifier stage includes five p-channel transistors.

A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.

A Controller Area Network, CAN, transceiver comprising: two terminals for coupling to a CAN bus; a transmitter arrangement configured to transmit signalling on the bus based on transmit data, the transmitter arrangement configured to drive the bus to a dominant state or recessive state based on the transmit signal; an impedance control device; a signalling detector to determine the length of time the transmit data comprises a logic zero prior to a transition to a logic one state and: based on the length of time being longer than a predetermined threshold, provide for control of an output impedance by the impedance control device in accordance with a first scheme; and based on the length of time being shorter than said predetermined threshold, provide for one of: control of said output impedance in accordance with a second scheme; and no control of the output impedance by the impedance control device.

Isolated circuit systems are provided. The systems include a primary side circuit and a secondary circuit, electrically isolated from each other. The primary side and secondary side circuits each utilize a direct current (DC) reference signal. The primary side circuit may use the DC reference signal in a modulation operation. The secondary side circuit may use the DC reference signal in a demodulation operation. The DC reference signal may be sent from the primary side circuit to the secondary side circuit, or from the secondary side circuit to the primary side circuit.