A communication circuit includes first and second communication nodes including first and second control chips, respectively, and first and second communication chips connected to the first and second control chips, respectively. The first and second communication chips are connected to each other through first and second signal lines, and are configured to transmit a differential signal. The first communication chip includes an output port to output a level signal obtained from the differential signal to the first control chip. The communication circuit further includes a voltage division assembly connected to the first and second signal lines, and configured to cause a voltage value of the first signal line to be higher than that of the second signal line when the first and second signal lines are in idle state. The first control chip includes a detection port connected to the output port to acquire the level signal.

Disclosed is a driver of an ethernet transmitter and a control method therefor. The driver has a first output port and a second output port connected to an ethernet receiver through a transmission line, and comprises: a signal conversion module for converting differential current signals into a first voltage signal and a second voltage signal; a first driving module adjusting a swing of the first voltage signal, to obtain a first output signal having a voltage equal to the first voltage signal; a second driving module adjusting a swing of the second voltage signal, to obtain a second output signal having a voltage equal to the second voltage signal. An architecture having a relatively small area is realized, and the ethernet transmitter meets the requirement on a large output swing in 10BASE-T mode.

A semiconductor device according to the present disclosure includes: a first output terminal and a second output terminal; a first driver that has a first positive terminal coupled to the first output terminal and a first negative terminal coupled to the second output terminal, and outputs a differential signal corresponding to a first signal from the first positive terminal and the first negative terminal; and a second driver that has a second positive terminal coupled to the second output terminal and a second negative terminal coupled to the first output terminal, and outputs a differential signal corresponding to the first signal from the second positive terminal and the second negative terminal.

A multi-level signal transmitter includes an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.

A transceiver device for a bus system. The transceiver device includes first and second bus terminals for connection to first and second signal line of the bus system, and a transmitting unit for outputting a bus transmission signal to the first and second bus terminals. The transceiver device includes an input connection for receiving a transmission input signal useable for controlling an operating state of the transmitting unit, and a detection device, which to detect the presence of a first predefinable condition and, if the first predefinable condition is present, to interconnect the first and second bus terminals via a predefinable electrical resistance for a predefinable first period of time.

A transmitter circuit receives a PWM input signal and a clock signal. A logic circuit generates a control signal as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than a half clock period of the clock signal. A tri-state transmitter receives the PWM input signal and the control signal, and produces first and a second output signals at first and second transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage and a reference voltage. An output control circuit is sensitive to the control signal and is coupled to the first and second transmitter output nodes.

A phase shifter includes functional actively controlled phase-shift elements formed with TSVs. The phase shifter may include plural phase shifter elements each including: a signal line including a signal line through-substrate-via (TSV) in a substrate; a ground return line including a ground return line TSV in the substrate; a capacitance control line including a capacitance control line TSV in the substrate; and an inductance control line including an inductance control line TSV in the substrate, wherein the phase shifter element has one of a first phase shift and a second phase shift, different from the first phase shift, based on a capacitance and an inductance of the signal line TSV.

A semiconductor integrated circuit has a reception circuit configured to receive a strobe signal of which a logic is intermittently switched in synchronization with a data signal, an output circuit configured to extract a low frequency component including at least a DC component of the strobe signal received by the reception circuit and to output a first signal, and a comparison circuit configured to compare a signal level of the first signal with a threshold level. The reception circuit is configured to change a boost amount of a high frequency component different from the low frequency component of the strobe signal based on a comparison result obtained by the comparison circuit.

According to one embodiment, in a semiconductor integrated circuit, a sampler is connected to an output node of a summer circuit. A shift register is connected to an output node of the sampler and includes K stages of registers, K being an integer that is equal to or larger than 3. To a control circuit, output nodes of respective registers of N-th to M-th stages among the K stages of registers are connected, N being an integer larger than 1 and smaller than K, M being an integer larger than N and equal to or smaller than K. A first switch includes one end connected to the output node of the summer circuit. A correction circuit includes a first control node that is connected to the control circuit through a first feedback line and an output node to which a second end of the first switch is connected.

A differential communication circuit is connected to a communication line formed of a positive communication line and a negative communication line for differential communication. The differential communication circuit includes: a series circuit that includes a resistor element and a connection switch. The resistor element is connected between the positive and negative communication lines when the connection switch is turned on. The circuit also includes a transmission unit that is configured to output a differential signal to the communication line and a controller that is configured to change impedance of the communication line by turning on the connection switch in a period during which the transmission unit does not output the differential signal.