An image sensor, comprising a pixel region in which a plurality of pixel units are arranged, each pixel unit having first and second photoelectric conversion portions, a first output portion that outputs, outside of the image sensor, a first signal based on a signal from the first photoelectric conversion portion of the pixel units, and a second output portion that outputs a second signal based on a signal from the first photoelectric conversion portion and a signal from the second photoelectric conversion portion of the pixel units, wherein output of the first signal from the first output portion and output of the second signal from the second output portion are performed in parallel.

A multiple-column-per-channel image CCD sensor utilizes a multiple-column-per-channel readout circuit including connected transfer gates that alternately transfer pixel data (charges) from a group of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at multiple times the line clock rate to pass the image charges to the shared output circuit. A symmetrical fork-shaped diffusion is utilized in one embodiment to merge the image charges from the group of related pixel columns. A method of driving the multiple-column-per-channel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the multiple-column-per-channel CCD sensor is also described.

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

A solid-state imaging device of an embodiment includes plural first transfer gate electrodes, plural second transfer gate electrodes, and plural fixed gate electrodes. The first transfer gate electrodes are such that the respective first transfer gate electrodes are placed in a charge transfer unit to correspond to single light receiving sections, and a control signal 1 is applied. The second transfer gate electrodes are such that the respective second transfer gate electrodes are placed in a charge transfer unit to correspond to the single light receiving sections, and a control signal 2 that differs in phase from the control signal 1 for transferring plural charges is applied. The respective fixed gate electrodes are such that the respective fixed gate electrodes are placed between the first and the second transfer gate electrodes corresponding to the single light receiving sections in the charge transfer unit, and a fixed voltage is applied.

An electronic imaging system for a digital camera or imaging device includes a secondary filter having a plurality of filter openings. Each of the filter openings configured to align with a respective light sensor positioned in a grid of light sensors on a CCD. Light filtering media located in the filter openings is employed to reduce light transmitted to the light sensors to either prevent overloads of the sensors or to calculate a corrected light sensor output from a light sensor positioned adjacent an overloaded light sensor.

A solid-state imaging device is provided that includes a pixel array with unit pixels. Each unit pixel includes, among other things, first and second photoelectric conversion portions; an electric charge accumulating portion that accumulates charges produced by the second photoelectric conversion portion, a counter electrode of the electric charge accumulating portion being connected to a variable voltage power source; and a charge-to-voltage conversion portion. For at least a part of a time period for which charges produced by the second photoelectric conversion portion are accumulated in the electric charge accumulating portion, a drive portion that controls an operation of the unit pixel causes a voltage of the variable voltage power source to be lower than that when a signal based on the charges accumulated in the electric charge accumulating portion is read out.

An image sensor is provided that includes a pixel array divided into a plurality of pixel groups. Each pixel group is clocked by a respective plurality of horizontal-register clocks. Clock signals for the image sensor are adjusted. Adjusting the clock signals includes phase-shifting each plurality of horizontal-register clocks by a respective phase delay of a plurality of phase delays. The phase delays are evenly spaced and are spaced symmetrically about zero. With the clock signals adjusted, a target is imaged using the image sensor.

An image-capturing device includes an infrared light source configured to emit infrared light, and a solid-state image-capturing device including a plurality of first pixels configured to convert visible light into signal charge and a plurality of second pixels configured to convert infrared light into signal charge, the plurality of first pixels and the plurality of second pixels being arranged on a semiconductor substrate in a matrix. The solid-state image-capturing device outputs, during the same single frame scanning period, a first signal obtained from the plurality of first pixels, a second signal obtained from the plurality of second pixels during a period of time when the infrared light is emitted, and a third signal obtained from the plurality of second pixels during a period of time when the infrared light is not emitted.

A pixel sensor element (200) including a photodetector (201) and a storage assembly having N storage arrays (205), each having an input shift register (207) and an output shift register (215) each with a number M of storage cells arranged in a column, and a storage shift register (207) to the output shift register (215). A number N of independently driveable signal transfer regions (203) transfer the signal from the photodetector (201) to a first cell (210) of one of a respective one of the input shift registers (207). A number N of signal read-out regions (219) read the signal from a last cell (217) of a respective one of the output shift registers (215). N is 2 or more. M is 1 or more. P is 1 or more. Image sensors, imaging devices, storage assemblies, and methods are also provided.

An imaging sensor having a pixel array with a separate analog-to-digital conversion (ADC) circuit coupled on an input side to each column line and on an output side to a separate M-bit wide digital memory circuit and a column data readout circuit comprising N M-bit data shifters. Each M-bit data shifter has an M-bit wide output, and single pole double throw (SPDT) switches whose common terminals provide inputs to the M-bit data shifters, wherein a first switch state of the SPDT switches connects the input of their associated M-bit data shifters to their associated M-bit wide digital memory circuits and wherein a second switch state of the SPDT switches connects the input of their associated M-bit data shifters to an M-bit wide output bus from an adjacent M-bit data shifter.