The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by a time ratio of the line time difference and the frame period. The line time difference of the TDI sensor is changeable without changing the separation space.

Image sensor circuitry comprising an image sensor and method for supporting reduction of laser speckle effects in a digital image. Per each pixel position (x, y) of at least a subregion of the image sensor, the image sensing circuitry: Assigns to said pixel position (x,y) a predefined pixel window (w) comprising said pixel position (x,y) and one or more of its closest neighboring pixel positions. Obtains first pixel values for each pixel located within said predefined pixel window (w), said first pixel values resulting from the same exposure and corresponding to sensed light from this exposure. Combines the obtained first pixel values into a single, second pixel value according to a predefined combination function. The digital image is provided based on the second pixel values.

To output event information at high sensitivity and high speed with a simple configuration. An imaging device includes: a plurality of pixels each having a plurality of photoelectric conversion elements that photoelectrically converts incident light to generate an electric signal; a detecting section that outputs a detection signal in a case where an absolute value of a change amount of the electric signal in a pixel of the plurality of pixels exceeds a predetermined threshold; a signal processing section that performs predetermined signal processing on the basis of the detection signal output from the detecting section; an AZ output section that outputs an auto-zero signal for initializing the detecting section; a time code generator that outputs a time code changing at a predetermined cycle; a first holding circuit that holds the time code output from the time code generator when the auto-zero signal is output; a second holding circuit that holds the time code output from the time code generator when the detection signal is output; and a transfer section that transfers the time code held in the first holding circuit and the time code held in the second holding circuit to the signal processing section in association with each other.

To output event information at high sensitivity and high speed with a simple configuration. An imaging device includes: a plurality of pixels each having a plurality of photoelectric conversion elements that photoelectrically converts incident light to generate an electric signal; a detecting section that outputs a detection signal in a case where an absolute value of a change amount of the electric signal in a pixel of the plurality of pixels exceeds a predetermined threshold; a signal processing section that performs predetermined signal processing on the basis of the detection signal output from the detecting section; an AZ output section that outputs an auto-zero signal for initializing the detecting section; a time code generator that outputs a time code changing at a predetermined cycle; a first holding circuit that holds the time code output from the time code generator when the auto-zero signal is output; a second holding circuit that holds the time code output from the time code generator when the detection signal is output; and a transfer section that transfers the time code held in the first holding circuit and the time code held in the second holding circuit to the signal processing section in association with each other.

Image quality is to be improved in a solid-state image pickup element that performs time delay integration. A correlated double sampling circuit generates a frame in which a predetermined number of lines each including a plurality of digital signals are arranged. A TDI frame memory retains a (K−1)-th frame generated before a K-th frame. A time delay integration circuit performs time delay integration processing of adding the line having a predetermined address in the K-th frame and the line having an address at a certain distance from the predetermined address in the (K−1)-th frame.

Disclosed is a linear array ultra-fast scanning x-ray imaging device. The linear array x-ray imaging device is single photon sensitive, operating in frame output mode and including a pixel array Application Specific Integrated Circuit including the readout pixel array. The ASIC includes digital control logic and sufficient memory to accumulate digital output frames in various modes of operation prior to output from the ASIC, permitting advanced imaging functionalities directly on the ASIC, while maintaining a dynamic range of 16 bits and single photon sensitivity. The effective or secondary frames output from the pixel array ASIC can be tagged with user provided external triggers synchronizing the effective frames to the x-ray beam energy and/or to the movement of the x-ray source or imaged object. This enables dual energy imaging and ultra-fast scanning, without complex and costly conventional photon counting x-ray imaging sensors. The system architecture is simpler and higher performance.

Disclosed is a linear array ultra-fast scanning x-ray imaging device. The linear array x-ray imaging device is single photon sensitive, operating in frame output mode and including a pixel array Application Specific Integrated Circuit including the readout pixel array. The ASIC includes digital control logic and sufficient memory to accumulate digital output frames in various modes of operation prior to output from the ASIC, permitting advanced imaging functionalities directly on the ASIC, while maintaining a dynamic range of 16 bits and single photon sensitivity. The effective or secondary frames output from the pixel array ASIC can be tagged with user provided external triggers synchronizing the effective frames to the x-ray beam energy and/or to the movement of the x-ray source or imaged object. This enables dual energy imaging and ultra-fast scanning, without complex and costly conventional photon counting x-ray imaging sensors. The system architecture is simpler and higher performance.

An x-ray weld inspection apparatus has at least one x-ray source, at least one x-ray detector, a motor arrangement configured to move the at least one x-ray source and the at least one x-ray detector substantially along a weld, and a control device. The control device comprises memory and at least one processing core, configured to control the motor arrangement to move the at least one x-ray source and the at least one x-ray detector during an x-ray weld scan substantially along the direction of the weld. At least one section of the weld is imaged at least twice during a single x-ray scan, producing at least two imaging data sets, respectively. An angle of incidence of x-rays at the at least one section of the weld is different for the imaging data sets.

An x-ray weld inspection apparatus has at least one x-ray source, at least one x-ray detector, a motor arrangement configured to move the at least one x-ray source and the at least one x-ray detector substantially along a weld, and a control device. The control device comprises memory and at least one processing core, configured to control the motor arrangement to move the at least one x-ray source and the at least one x-ray detector during an x-ray weld scan substantially along the direction of the weld. At least one section of the weld is imaged at least twice during a single x-ray scan, producing at least two imaging data sets, respectively. An angle of incidence of x-rays at the at least one section of the weld is different for the imaging data sets.

Provided are apparatus, methods and techniques to perform a readout of a plurality (N) of Time Delay and Integration (TDI) pixel registers to receive respective signal charges at a plurality (N) of sense nodes (SNs). The readout uses a plurality (N) of charge steering (CST) gates to steer and demultiplex respective charges from respective pixel registers to corresponding SNs. Output is provided from the SNs for producing respective digital values (e.g. through parallel conversion using ADCs). In an embodiment, charges are transferred vertically to the CSTs for demultiplexing horizontally to the SNs. The CSTs may be configured in a multi-stage configuration to assist with good charge transfer. The CSTs may be associated with a barrier implant to assist with proper charge steering.