An imaging device having pixels in a row which include: first pixel including a first photoelectric converter and a first transistor having a first control terminal; second pixel including a second photoelectric converter and a second transistor having a second control terminal; third pixel including a third photoelectric converter and a third transistor having a third control terminal; and fourth pixel including a fourth photoelectric converter and a fourth transistor having a fourth control terminal. The device further including input signal line, a signal for controlling the first to fourth transistors input to the signal line; first buffer circuit having a first input terminal coupled to the signal line, and a first output terminal coupled to the first and second control terminals; and second buffer circuit having a second input terminal coupled to the signal line and a second output terminal coupled to the second and third control terminals.

To improve the frame rate in an imaging apparatus that carries out still image recording and moving image display simultaneously. A pixel array includes an arrangement of a plurality of pixels. The plurality of pixels each include an internal memory. An exposure control unit carries out first exposure control in which captured data obtained by performing exposure to all the plurality of pixels together is retained in the internal memories of the pixels. The exposure control unit also carries out second exposure control in which captured data obtained by performing exposure to specific pixels of the plurality of pixels together is retained in the internal memories of the pixels.

A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.

A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.

An imaging device including a charge-holding section having a larger saturated charge amount is provided. The imaging device includes a first electrically-conductive type semiconductor substrate, a second electrically-conductive type photoelectric conversion section, a second electrically-conductive type charge-holding section, a transfer section, and a trench section. The semiconductor substrate includes a first surface and a second surface opposite thereto. The photoelectric conversion section, embedded in the semiconductor substrate, generates charges corresponding to a light reception amount by photoelectric conversion. The charge-holding section, embedded in the semiconductor substrate, holds the charges generated in the photoelectric conversion section. The transfer section transfers charges from the photoelectric conversion section to a transfer destination. The trench section extends in a thickness direction from the first surface toward the second surface in the charge-holding section. The trench section includes a first base and a first electrically-conductive type first semiconductor layer provided to cover the first base.

The present disclosure provides a pixel collection circuit which at least includes a photoelectric detection unit, an optical flow information timing trigger unit, an optical flow information timing control unit, an optical flow information timing unit and a row selection output unit. The present disclosure further provides an optical flow sensor including the pixel collection circuit, and an optical flow and image information collection system.

A detection substrate, a noise reduction method therefor and a detection device are disclosed. The detection substrate includes a base substrate, the base substrate including a noise reduction region; a plurality of first photosensitive devices in the noise reduction region; a plurality of reading lines and a plurality of scanning lines, where the plurality of reading lines and the plurality of scanning lines are arranged in different layers from the plurality of first photosensitive devices, and the plurality of reading lines and the plurality of scanning lines are in different layers and crossing over each other; and a plurality of first transistors in the noise reduction region, where the first transistor is disconnected from at least one of the first photosensitive device, the reading line or the scanning line.

A detection substrate, a noise reduction method therefor and a detection device are disclosed. The detection substrate includes a base substrate, the base substrate including a noise reduction region; a plurality of first photosensitive devices in the noise reduction region; a plurality of reading lines and a plurality of scanning lines, where the plurality of reading lines and the plurality of scanning lines are arranged in different layers from the plurality of first photosensitive devices, and the plurality of reading lines and the plurality of scanning lines are in different layers and crossing over each other; and a plurality of first transistors in the noise reduction region, where the first transistor is disconnected from at least one of the first photosensitive device, the reading line or the scanning line.

An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.

An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.