Patent classifications
H04N25/7795
SEMICONDUCTOR INTEGRATED CIRCUIT
Provided are a semiconductor integrated circuit and an imaging device capable of reducing power consumption without complicating a configuration of oscillation control.
A semiconductor integrated circuit includes an oscillator that generates an oscillation signal whose oscillation frequency is discretely adjustable on the basis of a digital control input signal, an oscillation controller that generates the digital control input signal, and an intermittent controller that generates an intermittent control signal and supplies the intermittent control signal to the oscillation controller so that the oscillation controller intermittently updates the digital control input signal.
SOLID-STATE IMAGING APPARATUS, IMAGING APPARATUS, AND DISTANCE-MEASURING IMAGING APPARATUS
A solid-state imaging apparatus includes a pixel circuit that outputs a pixel signal and a negative feedback circuit. The negative feedback circuit includes a sample and hold circuit (hereinafter SH circuit) that samples and holds the pixel signal, and a feedback amplifier that negatively feeds back, to the SH circuit, a feedback signal according to a difference between the pixel signal from the pixel circuit and an output signal from the SH circuit.
SOLID-STATE IMAGING DEVICE AND ELECTRONIC INSTRUMENT
To reduce the number of wirings through which transmission and reception are made between chips.
The solid-state imaging device includes a first substrate including a pixel array unit in which a plurality of pixels is arranged, each of the plurality of pixels including a photoelectric conversion unit, and the first substrate includes a first wiring through which an imaging pixel signal is transmitted, the imaging pixel signal being read from two or more of the pixels arranged in a first direction in the pixel array unit, a second wiring through which a reset voltage for initializing the first wiring is supplied, and a first switching circuit configured to switch whether or not to short-circuit the first wiring and the second wiring.
IMAGE SENSOR INCLUDING POWER MANAGEMENT UNIT FOR NOISE REDUCTION USING CHOPPING OPERATION AND OPERATION, METHOD THEREOF
An image sensor includes a pixel array including a plurality of pixel groups arranged in a plurality of rows and columns, the plurality of pixel groups configured to convert a light into electrical signals and to generate pixel signals, a row driver configured to generate a plurality of control signals for controlling the rows of the pixel array, and one or more power management devices configured to generate a power supply voltage for generating the plurality of control signals based on an input signal, and supply the power supply voltage to the row driver. Each of the one or more power management devices includes a first chopping circuit configured to modulate the input signal, an amplifier configured to generate an output signal based on the modulated input signal, and a second chopping circuit configured to demodulate the output signal and to modulate a noise caused by the amplifier.
FIXED PATTERN NOISE REDUCTION IN IMAGE SENSORS OPERATED WITH PULSED ILLUMINATION
Fixed pattern noise (FPN) reduction techniques in image sensors operated with pulse illumination are disclosed herein. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to first charge at a first floating diffusion, the first charge corresponding to first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to second charge at the second floating diffusion, the second charge corresponding to second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.
FIXED PATTERN NOISE REDUCTION IN IMAGE SENSORS OPERATED WITH PULSED ILLUMINATION
Fixed pattern noise (FPN) reduction techniques in image sensors operated with pulse illumination are disclosed herein. In one embodiment, a method includes, during a first sub-exposure period of a frame, (a) operating a first tap of a pixel to capture a first signal corresponding to first charge at a first floating diffusion, the first charge corresponding to first light incident on a photosensor, and (b) operating a second tap of the pixel to capture a first parasitic signal corresponding to FPN at a second floating diffusion. The method further includes, during a second sub-exposure period of the frame, (a) operating the second tap to capture a second signal corresponding to second charge at the second floating diffusion, the second charge corresponding to second light incident on the photosensor, and (b) operating the first tap to capture a second parasitic signal corresponding to FPN at the first floating diffusion.
INTRAORAL IMAGE CAPTURING DEVICE
An intra-oral imaging device includes: an imager that detects radiation transmitted through an object while being placed in an oral cavity; and a controller that controls the imager while being placed outside the oral cavity. The imager includes an image sensor including a plurality of pixels for acquiring an image of the object. While power is being supplied to the controller, the controller supplies power to the image sensor in an imaging period during which the image sensor performs imaging and stops supplying the power to the image sensor in a standby period during which the image sensor is on standby.
Programmable phase generator for a radiation detector
A generator of phases of a detector integrates at least one elementary machine for interpreting a microcode stored in a register. Each elementary machine includes at least one control input having a logic level change detector. Each elementary machine also includes at least one phase output having a controlled switch, enabling to define the logic level of the phase output, and a controlled inverter enabling to toggle the logic level of the phase output. Further, each elementary machine includes at least one clock signal associated with a counter, and a unit for loading the instructions and the arguments stored in the register, the instructions being coded over 3 bits.
IMAGE SENSOR PERFORMING SELECTIVE MULTIPLE SAMPLING AND OPERATING METHOD THEREOF
Disclosed is an image sensor including a pixel array including a plurality of pixels, each of the pixels including a first photodiode and a second photodiode, each of which outputs a first pixel signal based on a first conversion gain using the second photodiode in a first period, outputs a second pixel signal based on a second conversion gain using the second photodiode in a second period, outputs a third pixel signal based on the first conversion gain using the first photodiode in a third period, and outputs a fourth pixel signal based on the second conversion gain using the first photodiode in a fourth period, an ADC circuit that performs sampling on a reset signal and an image signal of each of the first to fourth pixel signal. A sampling count and the number of sampling bits are adjusted differently from each of the first to fourth period.
IMAGING DEVICE AND ANALOG-TO-DIGITAL CONVERSION CIRCUIT
An imaging device of the present disclosure includes a first pixel circuit and a generation circuit. The first pixel circuit includes a first light-receiving circuit, a first comparator, a first control circuit, and a first latch circuit. The first light-receiving circuit is configured to generate a first pixel signal corresponding to the amount of received light. The first comparator is configured to generate a first comparison signal by comparing the first pixel signal with a first reference signal having a ramp waveform. The first control circuit is configured to generate a first comparison output signal by turning on and off an output of the first comparison signal on the basis of a first control signal. The first latch circuit is configured to latch a time code on the basis of transition of the first comparison output signal. The generation circuit is configured to generate the first control signal.