An active imaging system including a laser to illuminate a scene and an imaging device to receive returns reflected from the scene. The imaging device including an array of pixel circuits, each pixel circuit including a photodiode connected to multiple track and hold circuits and a timing circuit configured to operate the track and hold circuits in quick succession such that each track and hold circuit captures an information signal indicative of returns arriving during different successive time periods during a gate period and thus provides 3D image data based on the arrival times of returns from the scene during the gate period.

An image sensor includes a pixel array, an analog-to-digital conversion circuit, and an image signal processor. A pixel of the pixel array generates a first analog signal based on a quantity of charge accumulated during a first exposure time and generate a second analog signal based on a quantity of charge accumulated during a shorter second exposure time. The analog-to-digital conversion circuit may generate a first digital signal based on the first analog signal and a first ramp signal and may generate a second digital signal based on the second analog signal and a second ramp signal. The image signal processor may generate image data based on the first and second digital signals. The first ramp signal may be different from the second ramp signal in terms of at least one of a ramping time or a ramping start voltage level.

An image sensor circuit includes a plurality of column analog/digital conversion circuits each including: first to n-th storage elements configured to respectively store first to n-th pieces of bit data that constitute analog/digital-converted data obtained by analog/digital-converting analog signals outputted by pixels, where n is an integer greater than or equal to 2; first to (n?1)-th transfer paths configured to respectively transfer the bit data stored in the first to (n?1)-th storage elements from the first to (n?1)-th storage elements to the second to n-th storage elements; and an n-th transfer path configured to transfer the bit data stored in the n-th storage element from the n-th storage element to outside the plurality of column analog/digital conversion circuits.

An image sensor array includes a pixel circuit that generates a pixel output signal, wherein an amplitude of the pixel output signal is related to an intensity of detected light. The pixel circuit passes the pixel output signal to a data signal line for a selection period. A current control capacitor supplies a current to the data signal line through a first electrode in the selection period. A ramp generator generates a voltage ramp signal and passes the voltage ramp signal to a second electrode of the current control capacitor in the selection period.

Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

A photoelectric conversion device including pixels, a scanning circuit and a controller is provided. The scanning circuit performs a driving operation including a first scan of causing the pixels to start an accumulation operation and a second scan of reading out signals from the pixels. The second scan includes first and second driving operations that are different in a length of a readout period. The controller is configured to supply, to the scanning circuit, a first synchronization signal for controlling the first scan and a second synchronization signal for controlling the second scan. A relationship between a cycle of the first synchronization signal and the second synchronization signal in the first driving operation and a cycle of the first synchronization signal and the second synchronization signal in the second driving operation is a non-integer multiple or a non-integral submultiple.

An imaging device has a sensor chip and a signal processing chip. The sensor chip includes a pixel array in which a plurality of pixels are arranged in a 2-dimensional matrix and a data output terminal group made up of a plurality of data output terminals which output analog signals of pixels for each pixel column of the pixel array. The signal processing chip includes a data input terminal group electrically coupled to the data output terminal group, a plurality of A/D converters which convert analog signals of pixels received by the data input terminal group into digital signals for each pixel column of the pixel array, and a control unit which controls operation of the plurality of A/D converters.

A stacked-type solid-state image sensor including a first semiconductor layer in which an imaging pixel portion is implemented, and a second semiconductor layer in which a digital signal processing unit is implemented, comprises a first timing control unit configured to generate a drive timing signal of the imaging pixel portion, an A/D converter configured to convert an analog signal output from each pixel of the imaging pixel portion into a digital signal, a second timing control unit configured to generate a drive timing signal of the A/D converter; and a status generation unit configured to receive an event signal generated by at least one of the first timing control unit and the second timing control unit and generate a status signal to restrict an operation of the digital signal processing unit.

A video signal transmission and reception system includes a first video signal receiver and a second video signal receiver in a video signal reception module and a video signal transmitter in a camera module. The video signal reception module includes the first video signal receiver, the second video signal receiver, and a central operation processor. A frame signal generated in the first video signal receiver is sent to a video signal transmitter of a first group and is output to the second video signal receiver. In addition, the frame signal generated in the first video signal receiver is input into the second video signal receiver and is sent to a video signal transmitter of a second group from the second video signal receiver.

A video signal receiver includes a clock signal receiver, a frame signal generator, and a frame signal transmitter. The clock signal receiver receives a camera video signal clock sent from a video signal transmitter in a camera module and outputs the clock to the frame signal generator. The frame signal generator generates a frame signal based on the clock received by the clock signal receiver and outputs the frame signal to the frame signal transmitter. The frame signal transmitter receives input of the frame signal output from the frame signal generator and sends the frame signal to the video signal transmitter of each camera module.