The present application discloses a circuit board and a method for manufacturing the same, and a terminal test device. The circuit board includes a base substrate, and a plurality of conductive lines on the base substrate, each of the plurality of conductive lines having one end configured to be connected with a signal output bus of a signal generator and the other end configured to be connected with a terminal. A fuse is connected in series in each conductive line, and a breaking current IT of the fuse, a maximum operating current I of the conductive line and a fault current IF of the conductive line satisfy: I<ITIF, where the breaking current IT of the fuse is a minimum current that causes the fuse to open.

A programmable circuit includes an array of printed groups of microscopic transistors or diodes having pn junctions. The devices are pre-formed and printed as an ink and cured. The devices have a proper orientation and a reverse orientation after settling on a conductor layer. The devices are connected in parallel within small groups. To neutralize the reverse-oriented devices, a sufficient voltage is applied across the parallel-connected diodes to forward bias only the devices having the reverse orientation. This causes a sufficient current to flow through each of the reverse-orientated devices to destroy an electrical interface between an electrode of the devices and the conductor layer to create an open circuit, such that those devices do not affect a rectifying function of the devices in the group having the proper orientation. An interconnection conductor pattern may then interconnect the groups to form complex logic circuits.

The invention provides a 3D printing method and product which makes use of a base module which comprises an electrical circuit, wherein the electrical circuit is incomplete. A 3D printed structure over the module completes the electrical circuit of the base module.

The present invention relates generally to electric circuit testing, building, or implementing using a breadboard style PCB. Aspects of the present invention include eliminating the need to use hookup wires when building and testing electric circuits on PCBs. In embodiments, a PCB system having rows and columns of signal tie points connected in a breadboard layout and using an embedded wire and a solder bridge to form partial connections between signal tie points. In embodiments, the embedded wire and solder bridge is capable of connecting a column of signal tie points. In embodiments, the embedded wire and solder bridge is capable of connecting a power rail to a signal tie point. Thus, a circuit can be implemented and tested by applying a small amount of solder to the solder bridge without the need for hookup wires.

An apparatus is provided with a component configured to be operatively coupled to an interface. In a first state, the component is mechanically and/or electrically attached to a substrate. Exposure of the interface to a thermal event that meets or exceeds a first temperature the resilient material is subject to undergo a state change to a second state. The state change includes a physical transformation of the interface, and includes a position change of the component.

In an example, monitoring circuitry (307) includes a first ( ) and second (502) coupling, at least one of which is to capacitively couple the monitoring circuitry to a monitored circuit on a product packaging (101). The monitored circuit has a resistance which is indicative of a status of a product (702) stored in the product packaging, and the monitored circuit is to be connected in series between the first coupling and the second coupling. The monitoring apparatus (300) may determine the resistance of the monitored circuit via the first and second couplings.

Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers, a cavity formed in at least one organic dielectric layer of the plurality of organic dielectric layers and a modular structure having first and second ports and a conductive member that is formed within the cavity. The conductive member provides modularity by being capable of connecting the first and second ports and also disconnecting the first and second ports.

A programmable circuit includes an array of printed groups of microscopic transistors or diodes having pn junctions. The devices are pre-formed and printed as an ink and cured. The devices have a proper orientation and a reverse orientation after settling on a conductor layer. The devices are connected in parallel within small groups. To neutralize the reverse-oriented devices, a sufficient voltage is applied across the parallel-connected diodes to forward bias only the devices having the reverse orientation. This causes a sufficient current to flow through each of the reverse-orientated devices to destroy an electrical interface between an electrode of the devices and the conductor layer to create an open circuit, such that those devices do not affect a rectifying function of the devices in the group having the proper orientation. An interconnection conductor pattern may then interconnect the groups to form complex logic circuits.

A flex circuit system according to an exemplary aspect of the present disclosure includes, among other things, a substrate, at least one bus bar mounted to the substrate and at least one voltage sense lead integrated with the substrate.

A patterned conductive layer on a flexible substrate includes pads for mounting an array of LEDs, conductive strips, and conductive tabs that couple the conductive strips to the pads. The desired circuit configuration is created by removing select tabs by punching holes or otherwise piercing the flexible substrate at the location of the tabs. In some embodiments, the patterned conductive layer is arranged to permit each LED to be mounted in either of two mirrored orientations, and in some embodiments, the patterned conductive layer is arranged to permit a separation between LEDs that is not predefined by the pattern. In some embodiments, the unmodified patterned conductive layer is arranged to provide a parallel circuit configuration, and the modified patterned conductive layer is arranged to provide a series or series-parallel configuration.