An opto-electric hybrid board includes: an electric circuit board including an insulation layer haying front arid back surfaces, arid electrical interconnect lines formed on the front surface of the insulation layer; and an optical waveguide having a substantially rectangular shape as seen in plan view and provided on the back surface of the insulation layer of the electric circuit board, with a metal layer therebetween. The optical waveguide has at least one end portion disposed in overlapping relation with the metal layer. The at least one end portion of the optical waveguide has corner portions. Each of the corner portions is radiused to have an arcuate shape or has a polygonal shape produced by arranging a plurality of obtuse-angled portions in a substantially arcuate configuration.

A plating-pattern plate is configured to transfer, to a substrate, a transfer pattern formed by electroless plating. The plating-pattern plate includes a transfer part having a transfer surface configured to have the transfer pattern be formed by electroless plating. The transfer surface of the transfer part contains iron and nickel. The plating-pattern plate provides a fine conductive pattern with stable quality.

A plating-pattern plate is configured to transfer, to a substrate, a transfer pattern formed by plating. The plating-pattern plate includes a base body and transfer parts disposed on the base body. Each of the transfer parts has a transfer surface configured to have the transfer pattern to be formed on the transfer surface by plating. The transfer parts are disposed electrically independent of one another on the base body. The plating-pattern plate provides a fine conductive pattern with stable quality.

A component carrier for carrying electronic components, wherein the component carrier comprises an at least partially electrically insulating core, at least one electronic component embedded in the core, and a coupling structure with at least one electrically conductive through-connection extending at least partially therethrough and having a component contacting end and a wiring contacting end, wherein the at least one electronic component is electrically contacted directly to the component contacting end, wherein at least an exterior surface portion of the coupling structure has homogeneous ablation properties and is patterned so as to have surface recesses filled with an electrically conductive wiring structure, and wherein the wiring contacting end is electrically contacted directly to the wiring structure.

The present invention relates to a method for reducing the optical reflectivity of a copper and copper alloy circuitry wherein a thin palladium or palladium alloy layer is deposited by immersion-type plating onto said copper or copper alloy. Thereby, a dull greyish or greyish black or black layer is obtained and the optical reflectivity of said copper or copper alloy circuitry is reduced. The method according to the present invention is particularly suitable in the manufacture of image display devices, touch screen devices and related electronic components.

An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 μm, 0.01 to 0.3 μm, and 0.01 to 0.5 μm, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 μm, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.

A ceramic circuit substrate is suitable for silver nanoparticle bonding of semiconductor elements and has excellent close adhesiveness with a power module sealing resin. A ceramic circuit substrate has a copper plate bonded, by a braze material, to both main surfaces of a ceramic substrate including aluminum nitride or silicon nitride, the copper plate of at least one of the main surfaces being subjected to silver plating, wherein: the copper plate side surfaces are not subjected to silver plating; the thickness of the silver plating is 0.1 μm to 1.5 μm; and the arithmetic mean roughness Ra of the surface roughness of the circuit substrate after silver plating is 0.1 μm to 1.5 μm.

A wiring substrate includes an insulating substrate, a conductor layer and an interlayer. The insulating substrate contains AlN. The conductor layer contains Cu. The interlayer is located between the insulating substrate and the conductor layer. In the interlayer, between a first region near the insulating substrate and a second region near the conductor layer, Cu concentration is higher in the second region than in the first region, and Al concentration is higher in the first region than in the second region.

A molded interconnect device that comprises a substrate and conductive elements disposed on the substrate is provided. The substrate comprising a polymer composition containing a polymer matrix that includes a thermotropic liquid crystalline polymer and from about 10 parts to about 80 parts by weight of a mineral filler per 100 parts by weight of the polymer matrix. The mineral filler has an average diameter of about 25 micrometers or less. The polymer composition contains copper in an amount of about 1,000 parts per million or less and chromium in an amount of about 2,000 parts per million or less, and further exhibits a surface resistivity of about 1×1014 ohm or more.

A method is provided for fabricating an electromagnetic shield for an electronic component on a PCB. The method includes providing a patterned metal layer; laminating the patterned metal layer with a second dielectric layer; forming a cavity in the second dielectric layer; applying a dry film resist over the second dielectric layer and the cavity; stripping the dry film resist from the second dielectric layer and portions of the cavity adjacent the cavity side walls; depositing a seed layer and metal over the second dielectric layer and the dry film resist; etching the preplating layer and the seed layer from top surfaces of a remainder of the dry film resist and the second dielectric layer; and stripping the remainder of the dry film resist, thereby exposing the preplating layer on the side walls of the cavity to provide the electromagnetic shield.