A wiring board includes a first interconnect layer, a first insulating layer covering the first interconnect layer, a second interconnect layer, thinner than the first interconnect layer, formed on the first insulating layer and having an interconnect density higher than that of the first interconnect layer, and a second insulating layer formed on the first insulating layer and covering the second interconnect layer. The first insulating layer includes a first layer including no reinforcing material, and a second layer including a reinforcing material. The first and second layers include a non-photosensitive thermosetting resin as a main component thereof. The first layer has a coefficient of thermal expansion higher than that of the second layer, and the second insulating layer includes a photosensitive resin as a main component thereof. The second interconnect layer includes an interconnect formed directly on and electrically connected to the first interconnect layer.

There is provided a copper foil provided with a carrier exhibiting a high peeling resistance against the developer in the photoresist developing process and achieving high stability of mechanical peel strength of the carrier. The copper foil provided with a carrier comprises a carrier; an interlayer disposed on the carrier, the interlayer having a first surface adjacent to the carrier and containing 1.0 atom % or more of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W and Ni and a second surface remote from the carrier and containing 30 atom % or more of Cu; a release layer disposed on the interlayer; and an extremely-thin copper layer disposed on the release layer.

A method of manufacturing a multilayer wiring board is disclosed, the method being capable of separating a substrate without large local warpage of the multilayer wiring layer and thereby improving the reliability of connection in the multilayer wiring layer. This method includes providing a laminated sheet having, in sequence, a substrate, a first release layer and a metal layer; forming a first wiring layer on the metal layer; alternately stacking insulating layers and wiring layers on the laminated sheet on which the first wiring layer is formed to give a laminate provided with a multilayer wiring layer; stacking a reinforcing sheet on the laminate provided with the multilayer wiring layer while interposing a second release layer; separating the substrate from the metal layer; and separating the reinforcing sheet from the laminate provided with the multilayer wiring layer to give the multilayer wiring board.

A display device includes a display substrate including a display area and a pad region, a first pad portion including a plurality of first pad terminals, the plurality of first pad terminals being arranged in a first direction, and a printed circuit board (PCB) including a base film and a second pad portion. The second pad is electrically connected to the first pad portion. The second pad portion includes a plurality of second pad terminals electrically connected to the plurality of first pad terminals, and a plurality of first test lines. The plurality of second pad terminals includes a plurality of sub-pad terminals. One of the plurality of first lines is connected to a first sub-pad terminal of the plurality of sub-pad terminals, and a second sub-pad terminal of the plurality of sub-pad terminals is not connected to any of the plurality of first lines.

A three-dimensional (3D) circuit structure includes a 3D insulating substrate having at least one circuit forming zone and at least one exposed contact forming zone; at least one circuit pattern portion provided on the 3D insulating substrate and having at least one circuit trace layout layer located in the circuit forming zone and at least one exposed contact located in the exposed contact forming zone and connected to the circuit trace layout layer; and an insulating encapsulation member covering at least the circuit forming zone and the circuit trace layout layer. With the insulating encapsulation member, the circuit trace layout layer is waterproof, dustproof, scratch-resistant, peeling-proof, secure for use, and compliant with safety codes of electrical insulation, enabling the 3D circuit structure in use to have stable electrical characteristics.

A three-dimensional (3D) circuit structure includes a 3D insulating substrate having at least one circuit forming zone and at least one exposed contact forming zone; at least one circuit pattern portion provided on the 3D insulating substrate and having at least one circuit trace layout layer located in the circuit forming zone and at least one exposed contact located in the exposed contact forming zone and connected to the circuit trace layout layer; and an insulating encapsulation member covering at least the circuit forming zone and the circuit trace layout layer. With the insulating encapsulation member, the circuit trace layout layer is waterproof, dustproof, scratch-resistant, peeling-proof, secure for use, and compliant with safety codes of electrical insulation, enabling the 3D circuit structure in use to have stable electrical characteristics.

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of pyrazole compounds and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features.

A method of forming a heat spreader on a printed circuit board (PCB), having a power dissipating component operably coupled thereto, includes attaching a thermally and electrically conductive structure, to a first side of the PCB to define a first PCB region that includes the component and a second PCB region without. The underside of the component is underfilled to electrically insulate its solder contacts. A first protective layer is applied to the second region of the PCB. A conductive plating membrane is deposited to the first region, the second region, and to the structure. A second protective layer is applied over a portion of the conductive plating membrane that overlays the second region, leaving exposed the rest of the conductive plating membrane. An electrically and thermally conductive layer is electroplated over the exposed areas of the conductive plating membrane, to form a heat exchanger within the first region.

There is provided a copper foil provided with a carrier exhibiting a high peeling resistance against the developer in the photoresist developing process and achieving high stability of mechanical peel strength of the carrier. The copper foil provided with a carrier comprises a carrier; an interlayer disposed on the carrier, the interlayer having a first surface adjacent to the carrier and containing 1.0 atom % or more of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W and Ni and a second surface remote from the carrier and containing 30 atom % or more of Cu; a release layer disposed on the interlayer; and an extremely-thin copper layer disposed on the release layer.

A printed circuit board includes: an insulating layer; a first circuit layer disposed on one surface of the insulating layer, and including a first circuit pattern and a first connection pad; and a surface treatment layer disposed on one surface of the first connection pad. The other surface of the first connection pad is covered by the insulating layer, and at least a portion of a side surface of the first connection pad is spaced apart from the insulating layer.