A circuit board (10, 10, 10) includes at last one insulating substrate layer (SL1, SL2, SL3, SL4, SL5) and a plurality of electrically conductive copper coats (C1, C2, C3) arranged on the at least one insulating substrate layer (SL1, SL2, SL3, SL4, SL5), wherein at least one of the electrically conductive copper coats (C1, C2, C3) is coated at least on both sides with a layer (HSI, HS2, HS3) made of a material for inhibiting electromigration, wherein on a layer (HS1, HS2) made of a material for inhibiting electromigration a further metal layer (M1, M2, M3, M3) is provided, which is in turn coated with a further layer (HS3, HS3) made of a material for inhibiting electromigration.

A manufacturing method for a circuit board and a circuit board are provided. The method includes steps: providing a substrate having a first metal layer; forming a patterned first opening on the first metal layer to expose the substrate; forming a patterned first dielectric layer on the substrate, the first dielectric layer is made of a photosensitive dielectric material and covers the first opening; photosensitizing the first dielectric layer to cure the first dielectric layer; forming a patterned second metal layer on the first metal layer; forming a patterned third metal layer on the second metal layer, and the third metal layer being adjacent to the first dielectric layer; removing a portion of the first metal layer not covered by the second metal layer; and forming a second dielectric layer on the substrate. A thickness of the third metal layer is greater than a thickness of the second metal layer.

A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.

The wired circuit board includes a metal supporting board, an insulating layer and a conductor layer disposed at one side in the thickness direction of the metal supporting board, a gold plate layer disposed at the other side in the thickness direction of the metal supporting board, and an adherence layer disposed between the metal supporting board and the gold plate layer. The material of the metal supporting board is a corrosion resistant alloy. In the adherence layer, gold and the metal contained in the corrosion resistant alloy are mixedly present.

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.

Encapsulated electronic modules having complex contact structures may be formed by encapsulating panels containing a substrate comprising pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within terminal holes and other holes drilled in the panel within the boundaries of the cut lines. Slots may be cut in the panel along the cut lines. The interior of the holes, as well as surfaces within the slots and on the surfaces of the panel may be metallized, e.g. by a series of processes including plating. Terminals may be inserted into the terminal holes and connected to conductive features or plating within the holes. A conductive element may be provided on the substrate to connect to a terminal. Alternatively solder may be dispensed into the holes for surface mounting.

A circuit board pad resonance control system includes a board. A signal transmission line is included on the board. A plurality of connector pads are positioned on the board. A first connector pad receives the signal transmission line adjacent a first end of that connector pad. The first connector pad includes a mounting surface that mounts directly to a coupling element that is configured to couple a subsystem to the board, and reduces a resonance that is produced by an open portion of a signal transmission path that is created when the coupling element is directly mounted to the mounting surface of the first connector pad in a first orientation. In a specific example, the mounting surface may include a plurality of protrusions, a plated surface, and/or a mask that reduces the conductivity of the connector pad which reduces signal integrity issues due to resonance.

In a described example, a method is described including: depositing a zinc seed layer on a substrate; forming a photoresist pattern on the zinc seed layer, with openings in the photoresist pattern exposing portions of the zinc seed layer; electroplating a copper structure onto the exposed portions of the zinc seed layer; stripping the photoresist; annealing the substrate to form copper/zinc alloy between the copper structure and the substrate; and etching away the unreacted portions of the zinc seed layer.

A multilayer circuit board structure includes a first multilayer circuit board and a second multilayer circuit board. The first multilayer circuit board includes a first patterned circuit layer and a first dummy circuit layer. The first dummy circuit layer surrounds the first patterned circuit layer. The second multilayer circuit board is disposed on the first multilayer circuit board, and includes a second patterned circuit layer and a second dummy circuit layer surrounding the second patterned circuit layer. The first patterned circuit layer is bonded to the second patterned circuit layer and the first dummy circuit layer is bonded to the second dummy circuit layer. A hollow space is defined between the first multilayer circuit board and the second multilayer circuit board.

In a semiconductor device, protective films are formed on facing side surfaces of a plurality of circuit patterns and a plating process or the like is not performed on parts aside from the side surfaces where the protective films are formed. This means that when semiconductor elements and contact elements are directly bonded via solder onto the plurality of circuit patterns, a drop-in wettability of the plurality of circuit patterns for the solder is avoided.