Disclosed are various embodiments relating to a circuit board included in an electronic device and, according to one embodiment, the circuit board can comprise: at least one wire included on the circuit board, at least one conductive structure arranged on the circuit board in order to reinforce the circuit board, and arranged in order to electrically connect the at least one wire; and at least one conductive member included on the circuit board, and electrically connecting the at least one wire with the at least one conductive structure, and additional other various embodiments are possible.

An article includes a solid circuit die on a first major surface of a substrate, wherein the solid circuit die includes an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads; a guide layer including an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; and a conductive particle-containing liquid in at least some of the microchannels. Other articles and methods of manufacturing the articles are described.

A drive backboard includes: a first conductive layer including bonding pins and first connecting lines, an insulating layer including first via holes and second via holes, a second conductive layer including connecting electrodes and second connecting lines and a conductive protective layer including first protective structures and second protective structures. The first via hole exposes the bonding pin, one end of a first connecting line electrically connects a bonding pin, and the other end reaches the second via hole. One end of a second connecting line electrically connects a connecting electrode, and the other end electrically connects the first connecting line through the second via hole. The first protective structure covers the bonding pin, and the second protective structure covers the second connecting line formed at the position of the second via hole. The pattern of the conductive protective layer is complementary to the pattern of the insulating layer.

An electronic package is provided, which includes: a substrate, an electronic element disposed on the substrate, and an antenna structure disposed on the substrate. The antenna structure has a base portion and at least a support portion, the base portion including a plurality of openings and a frame separating the openings from one another, and the support portion supporting the base portion over the substrate. Therefore, no additional area is required to be defined on a surface of the substrate, and the miniaturization requirement of the electronic package is thus met.

A manufacturing method of a circuit board and a stamp are provided. The method includes the following steps. A circuit pattern and a dielectric layer covering the circuit pattern are formed on a dielectric substrate. A conductive via connected to the circuit pattern is formed in the dielectric layer. A photoresist material layer is formed on the dielectric layer. An imprinting process is performed on the photoresist material layer using a stamp to form a patterned photoresist layer, wherein the pressing side of the stamp facing the circuit pattern becomes sticky when subjected to pressure so as to catch photoresist residue from the photoresist material layer in the imprinting process. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed.

A circuit board includes a base layer, an electrode layer formed on the base layer, a passivation layer formed on the electrode layer while opening a part of the electrode layer, and a surface treatment layer formed on the open surface of the electrode layer. The surface treatment layer may contain 70 to 40% of copper and 30 to 60% of nickel.

The invention concerns a display device including a transfer substrate (1010) including electric connection elements (L1, L2, C1, C2, P1, P2, P3, P4), and a plurality of semiconductor chips, wherein the transfer substrate (1010) includes an insulating plate, the electric connection elements of the substrate being formed by printing, on a surface of said plate, of a first conductive level, followed by an insulating level, followed by a second conductive level, the electric connection elements of the substrate including: a plurality of first conductive tracks (L1, L2) formed in the first conductive level; a plurality of second conductive tracks (C1, C2) formed in the second conductive level; and for each chip of the device, a plurality of electric connection areas (P1, P2, P3, P4) respectively connected to connection terminals of the chip, said areas being all formed in the second conductive level.

A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.

A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.

A circuit board is manufactured by mounting a first circuit layer, mounting a conductive bump on the first circuit layer, covering the first circuit layer with a first dielectric layer which exposes the conductive bump, mounting a second dielectric layer on the first dielectric layer with a second dielectric layer opening that exposes the conductive bump, and finally, mounting a second circuit layer on the surface of the second dielectric layer and in the second dielectric layer opening. Since the surface roughness of the second dielectric layer and the second dielectric layer opening is low, it is unlikely to form nano voids between the second dielectric layer and the second circuit layer, and the second circuit layer may be attached to the second dielectric layer firmly, which is an advantage for fine line circuit disposal.