A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

An apparatus for manufacturing a printed circuit board having a substrate with an upper and a lower surfaces is disclosed. The apparatus is configured to implement a stacking operation disposing a first insulating material and a second insulating material on the upper and the lower surfaces of the substrate respectively. The apparatus includes a stacking operation table with a first and a second sides, a first measuring table and a first transporting device. The first measuring table is disposed adjacent to the first side of the stacking operation table, and has a first and a second image sensing elements disposed at a pair of diagonal corners. The first transporting device is movably disposed on a location higher than the stacking operation table and the first measuring table to transport the first and the second insulating materials to the first measuring table and then to the stacking operation table sequentially.

A multilayer ceramic substrate includes: a plurality of ceramic layers 300a, 300b stacked together; a via hole 400a, 400b provided in each of the plurality of ceramic layers, the via holes of the plurality of ceramic layers being connected together in a layer stacking direction of the plurality of ceramic layers; a via wire 406a, 406b including an electrical conductor filled into each of the via holes; a first conductor 404a, 404b provided on an upper surface of at least one of the plurality of ceramic layers, the first conductor having an annular or partially annular shape surrounding the via wire; and a second conductor 403a, 403b including a first portion and a second portion, the first portion being located outside the first conductor on the upper surface of the at least one ceramic layer, the second portion overlying the first conductor, and an inner rim of the second portion being located outside an inner rim of the first conductor, wherein a thickness of the first conductor 404a, 404b is greater than a thickness of the second conductor 403a, 403b.

The present disclosure relates to a multilayer ceramic substrate preparation method. The multilayer ceramic substrate preparation method according to the present disclosure includes firing a plurality of ceramic green sheets, to create a plurality of ceramic thin films; forming a via hall in each of the plurality of ceramic thin films; filling the via hall of the plurality of ceramic thin films with conductive paste, and heat treating the via hall filled with the conductive paste, to form a via electrode; printing a pattern on a cross section of each of the plurality of ceramic thin films, and heat treating the printed pattern, to form an inner electrode; applying a bonding agent on the cross section of each of the ceramic thin films excluding an uppermost ceramic thin film of the plurality of ceramic thin films; aligning and laminating each of the plurality of ceramic thin films such that each of the plurality of ceramic thin films is electrically connected through the via electrode and the inner electrode; and firing or heat treating the laminated plurality of ceramic thin films.

A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.

A method of manufacturing a multi-layer for a probe card comprises providing first contact pads on an exposed face of a first dielectric layer and second contact pads on an exposed face of a last dielectric layer. Each dielectric layer is laser ablated to realize pass-through structures and the pass-through structures are conductively filled to realize conductive structures. The dielectric layers are superimposed in a way that each conductive structure contacts a corresponding conductive structure of a contiguous dielectric layer in the multi-layer and forms conductive paths electrically connected the first and second contact pads. The second contact pads having a greater distance between its symmetry centers than the first contact pads, the multi-layer thus performing a spatial transformation between the first and second contact pads connected through the connective paths.

An electrical assembly having an electrical device electrically connected to a multilayer bus board, which has a multilayer stacked assembly that includes a plurality of electrically conductive layer structures and at least one dielectric layer structure disposed between an adjacent pair of the conductive layer structures. A frame formed of a dielectric material encapsulates at least a portion of the multilayer stacked assembly and mechanically maintains the conductive layer structures and the dielectric layer structure in secure aligned abutting relation.

A multilayer wiring board having a high degree of freedom of wiring design and realizing high-density wiring, and a method to simply manufacture the multilayer wiring board is provided. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically connected to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 m. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via.

A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.

In fabricating a wiring structure, a first wiring is formed on a substrate. First and second light sensitive insulation layers that are reactive to light of first and second wavelength ranges, respectively, are sequentially formed on the first wiring. First and second exposing processes are performed using the light of the first and second wavelength ranges, respectively, to form first and second exposed portions in the first and second light sensitive insulation layers, respectively. The first and second exposed portions are removed by a developing process to form a hole and an opening, respectively. The hole and the opening extend through the first and second light sensitive insulation layers, respectively, to be connected to one another. A conductive layer is formed in the hole and in the opening, and is planarized to form a first via and a second wiring in the hole and in the opening, respectively.