A process includes utilizing a pin array that includes multiple segmented pins for forming selectively plated through holes. The process includes forming a PCB laminate structure that includes multiple spinel-doped core layers and multiple through holes. Each spinel-doped core layer includes a heat-activated spinel material incorporated into a dielectric material. The process includes aligning individual segmented pins of a pin array with corresponding through holes of the PCB laminate structure, where each segmented pin includes heated segment(s) and insulating segment(s). The process includes inserting the segmented pins of the pin array into the corresponding through holes and generating heat within each heated pin segment that is sufficient to form metal nuclei sites in selected regions of the spinel-doped core layers adjacent to portions of the through holes that contain the heated pin segments. The metal nuclei sites function as seed layers to enable formation of selectively plated through holes.

A component-embedded resin substrate (1) includes a plurality of resin layers (2) made of a first resin and laminated on one another, and a component (3) arranged to be surrounded by each resin layer (2) in a first group (8) which is a group of two or more resin layers arranged successively in a thickness direction included in the plurality of resin layers (2). An auxiliary resin portion (9) made of a second resin different from the first resin is arranged to be in contact with and along at least one of surfaces of the component (3).

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

A method of making a printed circuit board and a printed circuit board including a plurality of plastic substrate parts having one or more first substrate parts each having at least one coupling means, and one or more second substrate parts each having at least one receiving means to receive the coupling mean. At least one of the plurality of plastic substrate parts is formed with a further structural element, and at least two of the plurality of plastic substrate parts are connected to each other through the at least one coupling means and the at least one receiving means. The connected substrate parts include a circuit.

A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

An electronic device includes a communication circuit electrically connected with a circuit board. The circuit board includes a first portion comprising a first layered structure in which a wiring layer and a first insulating layer are alternately positioned, and a second portion comprising a second layered structure in which the wiring layer and the first insulating layer are alternately positioned and a second insulating layer. At least one antenna patch is positioned on or within the second insulating layer. A conductive line penetrates the second layered structure and the second insulating layer and electrically connects the at least one antenna patch and the communication circuit. The first insulating layer has a first loss tangent value, and the second insulating layer has a second loss tangent value smaller than the first loss tangent value.

A printed circuit board with built-in vertical heat dissipation ceramic block, and an electrical assembly are disclosed. The electrical assembly includes the board and a plurality of electronic components. The printed circuit boards includes a dielectric material layer defining at least one through hole, at least one ceramic block corresponding to the through hole, at least one fixing portion for joining the ceramic block to the through hole of the dielectric material layer, a metal circuit layer provided on upper surfaces of the dielectric material layer and the ceramic block, and a high thermal conductivity layer provided on lower surfaces of the dielectric material layer and the ceramic block. The printed circuit board allows the location and size of the ceramic block to be modified according to requirements, so as to implement complicated circuit designs, achieve good effect of thermal conduction, control thermal conduction path, and reduce manufacturing cost.

A method of a circuit signal enhancement of a circuit board comprises the following steps: forming a first substrate body with a first signal transmission circuit layer and a second substrate body with a second signal transmission circuit layer; forming a first signal enhancement circuit layer and a second signal enhancement circuit layer on the first substrate body and the second substrate body; forming a third substrate body with a third signal transmission circuit layer and a fourth substrate body with a fourth signal transmission circuit layer on the carrier; separating the third substrate body and the fourth substrate body from the carrier; combining the first signal transmission circuit layer and the third signal transmission circuit layer through the first signal enhancement circuit layer; and combining the second signal transmission circuit layer and the fourth signal transmission circuit layer through the second signal enhancement circuit layer.

A method for manufacturing a flex inlay is provided. The method includes providing a flexible printed circuit having opposed surfaces. The method includes attaching components to a surface of the flexible printed circuit. The method includes applying a coverlay over at least one surface of the flexible printed circuit, wherein the coverlay is patterned to not cover any components attached to the surface of the flexible printed circuit. The coverlay at least in part forms an essentially planar surface of the flex inlay.

A printed circuit board (PCB) incorporates at least one damping layer or section. The at least one damping layer is incorporated in the PCB to absorb vibrations or oscillations that may be conveyed to the PCB. Such vibrations or oscillations may be generated by one or more electrical components coupled to the PCB. The damping layer is disposed to prevent the PCB from audibly vibrating when the electrical components associated with the PCB are caused to vibrate or pulsate under a voltage load.