A trace to be coupled to an input of a receiver, the trace including: a plurality of first portions; and a plurality of second portions alternately coupled in series with the first portions, the second portions having a width that is different from that of the first portions.

Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

Semiconductor packages, module substrates and semiconductor package modules having the same are provided. The semiconductor package module includes a module substrate provided with a plurality of signal wires on an upper surface thereof, a package substrate disposed on the module substrate, a semiconductor chip disposed on one surface of the package substrate, and a plurality of external connection terminals disposed on another surface of the package substrate.

A transmission line portion of a flat cable includes first regions and second regions connected alternately. In the first region, the transmission line portion is a flexible tri-plate transmission line including a dielectric element including a signal conductor, a first ground conductor including opening portions, and a second ground conductor which is a solidly filled conductor. In the second region, the transmission line portion is a hard tri-plate transmission line including a wide dielectric element including a meandering conductor, and a first ground conductor and a second ground conductor which are solidly filled conductors. A variation width of the characteristic impedance in the second region is larger than a variation width of the characteristic impedance in the first region.

A stretchable interconnect includes a plurality of electrically conductive traces formed as a complex pattern on an elastic substrate. The form of the electrically conductive traces is such that when the elastic substrate is in a relaxed, or non-stretched, state each of the electrically conductive traces forms a tortuous path, such as a waveform, along the elastic substrate. The tortuous path of the electrically conductive traces provides slack such that as the elastic substrate is stretched the slack is taken up. Once released, the elastic substrate moves from the stretched position to the relaxed, non-stretched position, and slack is reintroduced into the electrically conductive traces in the form of the original tortuous path.

A semiconductor package includes a package substrate including a first voltage substrate wire, an interposer substrate provided on the package substrate and including a first voltage interposer wire, a first semiconductor chip mounted on a top surface of the interposer substrate, and a voltage control chip provided on the top surface of the interposer substrate and laterally spaced apart from the first semiconductor chip, wherein the first semiconductor chip is electrically connected to the voltage control chip through the first voltage substrate wire, and wherein the first semiconductor chip is electrically connected to the voltage control chip through the first voltage interposer wire.

Disclosed are apparatus and methods for optical planar metrology of electrical components utilizing cross-sectioning techniques. A disclosed apparatus includes at least one predefined geometric shape or array composed of a material and disposed on a surface of the circuit board in proximity to an electrical component under test. The shape or array creates an optically measureable unique feature for each cross sectional plane created during the performance of optical planar metrology regardless of depth or overall planarity. The geometry of the shape or array ensures a unique cross-sectional profile for every plane and the material of the shape or array (e.g., copper or a similar material having equivalent optical properties) allows for optical visibility and differentiation from surrounding materials.

The present disclosure discloses a crystal oscillator circuit on a PCB. The crystal oscillator circuit includes a crystal oscillator including an input end, an output end, a first grounding end and a second grounding end; a first capacitor with one end connected to the input end; and a second capacitor with one end connected to the output end, wherein the first grounding end is connected to a first grounding hole, the second grounding end is connected to a second grounding hole, the other end of the first capacitor is connected to a third grounding hole, the other end of the second capacitor is connected to a fourth grounding hole. The present disclosure further discloses the PCB and a server.

A device is provided that includes a printed circuit board having a top surface, a first trace disposed directly on the top surface of the printed circuit board, and a second trace disposed directly on the top surface of the printed circuit board adjacent the first trace. A first metal dome is positioned over the first trace and is configured to block crosstalk between the first trace and the second trace.

A manufacturing method of the electronic device includes the following steps. A first electronic unit and a second electronic unit are provided on a carrier. An insulating layer is provided to surround the first electronic unit and the second electronic unit. The insulating layer is grinded to expose at least a portion of the first electronic unit and at least a portion of the second electronic unit. An offset verification is performed on at least one of the first electronic unit and the second electronic unit to obtain an offset result. A circuit structure is provided on the insulating layer according to the offset result. The circuit structure includes a first conductor layer and a second conductor layer. The first conductor layer includes a first trace and a second trace, and the first trace and the second trace are electrically connected via the second conductor layer.