The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole from a metal foil for an upper layer wiring pattern to an inner layer wiring pattern by using a conformal method or a direct laser method, and (2) a step of forming a via hole by forming electrolytic filling plating layers in the hole for a via hole, wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again, two or more times before the electrolytic filling plating layers block an opening of the hole for a via hole.

A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and defines a first cavity. The first cavity is defined by a first sidewall, a second sidewall, and a first surface of the dielectric layer. The first sidewall is laterally displaced from the second sidewall.

A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and defines a first cavity. The first cavity is defined by a first sidewall, a second sidewall, and a first surface of the dielectric layer. The first sidewall is laterally displaced from the second sidewall.

A Capacitive Micromachined Ultrasonic Transducer (CMUT) device including at least one CMUT element with at least one CMUT cell is formed. A patterned dielectric layer thereon including a thick and a thin dielectric region is formed on a top side of a single crystal material substrate. A second substrate is bonded to the thick dielectric region to provide at least one sealed micro-electro-mechanical system (MEMS) cavity. The second substrate is thinned to reduce a thickness of said second substrate to provide a membrane layer. The membrane layer is etched to form a movable membrane over said MEMS cavity and to remove said membrane layer over said top side substrate contact area. The thin dielectric region is removed from over said top side substrate contact area. A top side metal layer is formed including a trace portion coupling said top side substrate contact area to said movable membrane. From a bottom side surface of said first substrate, etching is performed to open an isolation trench around said single crystal material to form a through-substrate via (TSV) plug of said single crystal material at least under said top side substrate contact area which is electrically isolated from surrounding regions of said single crystal material.

A base substrate which prevents burrs generated during the cutting process includes: multiple conductive layers stacked in one direction with respect to the base substrate; at least one insulation layer being alternately stacked with said conductive layers and electrically separating said conductive layers; and a through-hole penetrating said base substrate covering said insulation layer at the contact region where said cut surface and said insulation layer meet during the cutting of said base substrate in accordance with a predetermined region of the chip substrate. A method of manufacturing the base substrate includes alternately stacking conductive layers and insulation layers and forming a through-hole.

A method for producing a printed circuit board is disclosed, In the method, a slot is formed in a substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. Then, the conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.

A wiring board includes: an inorganic insulating layer having a via hole formed so as to penetrate the inorganic insulating layer in a thickness direction thereof; a conductive layer disposed on the inorganic insulating layer; and a via conductor which adheres to an inner wall of the via hole and is connected with the conductive layer. The inorganic insulating layer includes a first section including a plurality of inorganic insulating particles partly connected to each other, and a resin portion located in gaps between the inorganic insulating particles, and a second section which is interposed between the first section and the via conductor, including a plurality of inorganic insulating particles partly connected to each other, and a conducting portion composed of part of the via conductor which is located in gaps between the inorganic insulating particles.

A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.

A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers; and at least one via configured for solder attachment to a connector lead of a surface mount connector, the at least one via including a conductive element that extends from an upper surface of the printed circuit board through one or more of the plurality of layers, the conductive element having a recess in a surface thereof. The recess is configured to receive a tip portion of the connector lead of the surface mount connector. The printed circuit board may have via patterns including signal vias and ground vias.

A mounting substrate includes a through-hole 13 formed in a substrate 10, a first land part 21, a second land part 31, a first component attaching part 22, a second component attaching part 32, a conductive layer 14, and a filling member 15 filled into a part of the through-hole 13. A shortest distance allowable value L.sub.0 from the center of the first land part 21 to a component 51 is determined on the basis of the volume V.sub.h of a part of the through-hole 15 positioned above a top surface of the filling member 15 on the side of the first land part 21, the length L.sub.1 of the component 51 to be mounted to the first component attaching part 22, and the maximum allowable value of the inclination of the component 51 to be mounted to the first component attaching part 22 relative to the first surface 11 of the substrate 10.