Depicted embodiments are directed to an Application Specific Electronics Packaging (ASEP) system, which enables the manufacture of additional products using reel to reel (68a, 68b) manufacturing processes as opposed to the batch processes used to currently manufacture electronic products and MIDs. Through certain ASEP embodiments, it is possible to integrate connectors, sensors, LEDs, thermal management, antennas, RFID devices, microprocessors, memory, impedance control, and multi-layer functionality directly into a product.

A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. Trace channels and apertures are formed into the catalytic laminate, electroless plated with a metal such as copper, filled with a conductive paste containing metallic particles, which are then melted to form traces. In a variation, multiple circuit board layers have channels formed into the surface below the exclusion depth, apertures formed, are electroless plated, and the channels and apertures filled with metal particles. Several such catalytic laminate layers are placed together and pressed together under elevated temperature until the catalytic laminate layers laminate together and metal particles form into traces for a multi-layer circuit board.

The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

Depicted embodiments are directed to an Application Specific Electronics Packaging (ASEP) system, which enables the manufacture of additional products using reel to reel (68a, 68b) manufacturing processes as opposed to the batch processes used to currently manufacture electronic products and MIDs. Through certain ASEP embodiments, it is possible to integrate connectors, sensors, LEDs, thermal management, antennas, RFID devices, microprocessors, memory, impedance control, and multi-layer functionality directly into a product.

Methods and systems are contemplated for making portions of electrical circuits with embedded electrical components, and the electrical circuits produced thereby. A layer of dielectric material is deposited over a substrate, and a cavity is formed in the dielectric material. An electrical component (e.g., integrated chip, etc.) is deposited in the cavity and covered by a further dielectric material, embedding the electrical component. Another cavity is formed in the further dielectric material, and a catalyst (e.g., electrolytic deposition catalyst, electroless deposition catalyst, etc.) is deposited over the further dielectric material and at least a portion of the electrical component. A conductor is then plated at the catalyst, preferably contacting the I/O ports of the electrical component.

A method for manufacturing electrically conductive structures, preferably conductive pathway structures using laser beams on a non-conductive carrier (LDS method), wherein a non-conductive carrier material is provided which contains at least one inorganic metal phosphate compound and at least one stabiliser finely distributed or dissolved therein, the carrier material is irradiated in regions by laser beams generating the electrically conductive structures in the irradiated regions.

The present invention provides for depositing a desired pattern (31) of magnetic material (30) on a non-magnetic substrate (20). Control of the deposition pattern (31) is achieved by use of a magnetised template (10) shaped to correspond to the desired deposition pattern. In use, the template (10) is placed behind the substrate (20). Subsequently, the front surface of the substrate (20) is exposed to a solution containing the magnetic material (30) to be deposited. The magnetic material (30) is attracted to the magnetised template (10) and consequently is deposited in a pattern (31) covering areas corresponding to the shape of the template (10).

A wiring substrate at which a metal wire is formed includes a substrate containing a resin as a main component and an organic substance having a hydroxyl group; and a metal plating layer constituting the metal wire. A formation portion of the metal wire at one surface of the substrate is rougher than a non-formation portion of the metal wire at the one surface of the substrate, and has the organic substance in a state of being embedded in the resin, and a catalyst. The wiring substrate with such a configuration can increase the adhesion of the metal wire to the substrate.