Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming bit lines on the base, and forming semiconductor channels on surfaces of the bit lines away from the base, the semiconductor channel including a first doped region, a channel region and a second doped region arranged sequentially; forming a first dielectric layer, the first dielectric layer surrounding sidewalls of the semiconductor channels, and a first gap being provided between parts of the first dielectric layer located on sidewalls of adjacent semiconductor channels on a same bit line; forming a second dielectric layer, the second dielectric layer filling up the first gaps, and a material of the second dielectric layer being different from a material of the first dielectric layer; removing a part of the first dielectric layer to expose sidewalls of the channel regions.

The semiconductor structure includes a first capacitive structure located on a substrate and first support columns. A plurality of first support columns are disposed on the substrate in parallel and spaced apart from each other, and are located in a same plane parallel to the substrate. The first capacitive structure includes a first lower electrode layer, a first dielectric layer and a first upper electrode layer. The semiconductor structure further includes a plurality of first segmentation trenches. The first segmentation trenches divide the first capacitive structure into a plurality of capacitors. A first insulation layer is disposed between the corresponding first lower electrode layers of the adjacent capacitors. The corresponding first upper electrode layers of the adjacent capacitors are electrically connected to each other.

The present disclosure provides a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method of a semiconductor structure includes: forming a plurality of cylindrical capacitors in an initial structure; removing part of the initial structure to form trenches, the trenches expose partial sidewalls of the cylindrical capacitors and a substrate of the initial structure; forming a dielectric layer, the dielectric layer at least covers an exposed surface of each of the cylindrical capacitors; forming a first top electrode, the first top electrode covers a surface of the dielectric layer; and forming a second top electrode, the second top electrode covers a surface of the first top electrode. In an axial direction of each of the cylindrical capacitors, the second top electrode formed in each of the trenches has a discontinuous part, and an air gap is formed in the discontinuous part of the second top electrode.

A semiconductor memory device comprises: a memory cell array including a word line stack including word lines vertically stacked; and a sub word line driver block including sub word lines disposed below an end portion of the word line stack, wherein the word lines and the sub word lines extend in directions, respectively, crossing each other.

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate, and a plurality of storage structures stacked on the substrate. Each of the plurality of storage structures includes: a first dielectric layer; at least one channel layer arranged in the first dielectric layer and extending in a first direction, the first dielectric layer being provided with a plurality of first grooves isolating the at least one channel layer; and a capacitor structure covering a sidewall and a bottom surface of each of the plurality of first grooves.

A method for forming a capacitor array structure includes the following operations. A base is formed, which includes a substrate, a stack structure located on the substrate and a mask layer located on the stack structure in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided. The stack structure is etched along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate. A conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer is formed. The conductive layer and the mask layer at a top surface of the stack structure are removed, and the conductive layer remaining in the capacitor hole forms a lower electrode.

A method of manufacturing a semiconductor device includes: providing a first process gas including oxygen and a second process gas including carbon and fluorine to a process chamber at a first flow rate ratio to etch an etch target layer; and providing the first process gas and the second process gas to the process chamber at a second flow rate ratio to passivate the etch target layer, wherein a flow rate of the first process gas is substantially constant.

Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

The invention discloses a dynamic random access memory (DRAM) device and a method of fabricating such DRAM device. The DRAM device according to the invention includes a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of transistors formed between the first isolation stripes and the second isolation stripes, a plurality of word lines, and a plurality of capacitors formed above the first isolation stripes and the second isolation stripes. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns in the longitudinal direction, and a plurality of rows in the transverse direction. The first isolation stripes and the second isolation stripes extend in the longitudinal direction. Each transistor corresponds to one of the columns and one of the rows. The transistors on one side of each first isolation stripe and the transistors on the other side of said one first isolation stripe are staggeredly arranged. Each word line corresponds to one of the columns and connects the gate conductors of the transistors along the corresponding column. Each capacitor corresponds to one of the transistors and connects the source region of the corresponding transistor.