Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

A semiconductor device includes a substrate, a gate feature, a gate spacer, and a dielectric layer. The gate feature is above the substrate and includes a gate electrode. The gate spacer is on a sidewall of the gate feature. The dielectric layer is in contact with the gate spacer and has a larger thickness than the gate electrode.

Present invention relates to a method of fabricating a semiconductor device that can facilitate the processes of etching a supporter and removing a mold layer. According to the present invention, a method of fabricating a semiconductor device semiconductor device comprises: sequentially forming a substructure over a substrate and a etch stop layer over the substructure; forming a stack structure of alternately stacked mold layers and supporter layers over the etch stop layer; forming a plurality of supporter holes in the stack structure exposing the etch stop layer; forming a sacrificial layer filling each of the plurality of the supporter holes; forming a plurality of lower electrode openings exposing the substructure by etching the sacrificial layer and the stack structure; and forming a lower electrode inside the plurality of lower electrode openings.

A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.

A method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line. Other embodiments, including structure independent of method, are disclosed.

A semiconductor device includes a first electrode on a substrate, a second electrode on the substrate, a dielectric layer structure between the first electrode and the second electrode, and a crystallization inducing layer between the dielectric layer structure and the first electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a second dielectric layer on the first dielectric layer and including a second dielectric material.

A method for fabricating a memory device includes: forming a first dielectric layer disposed on a substrate, and a first opening in the first dielectric layer; filling a lower portion of the first opening with a first conductive material layer; conformally forming a lining layer over sidewalls of an upper portion of the first opening and a top surface of the first conductive material layer; filling the upper portion of the first opening with a second conductive material layer; etching back the second conductive material layer and the lining layer to form a recess; conformally forming a protection layer on sidewalls and a bottom portion of the recess and a top surface of the first dielectric layer; forming a second opening that penetrates through the protection layer, the second conductive material layer, the lining layer and the first conductive material layer; forming a pair of contacts in the first opening.

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.

A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.