All-printed paper-based substrate memory devices are described. In an embodiment, a paper-based memory device is prepared by coating one or more areas of a paper substrate with a conductor material such as a carbon paste, to form a first electrode of a memory, depositing a layer of insulator material, such as titanium dioxide, over one or more areas of the conductor material, and depositing a layer of metal over one or more areas of the insulator material to form a second electrode of the memory. In an embodiment, the device can further include diodes printed between the insulator material and the second electrode, and the first electrode and the second electrodes can be formed as a crossbar structure to provide a WORM memory. The various layers and the diodes can be printed onto the paper substrate by, for example, an ink jet printer.

A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer.

There is provided a non-volatile memory device comprising: a substrate; a lower electrode disposed on the substrate; a resistance layer disposed on the lower electrode; and an upper electrode disposed on the resistance layer, wherein the resistance layer include a stack of a graphene oxide film and an iron oxide film, wherein a resistance value of the resistance layer varies based on a voltage applied to the upper electrode.

A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.

Electrical switching technologies employ the otherwise undesirable line defect in crystalline materials to form conductive filaments. A switching cell includes a crystalline layer disposed between an active electrode and another electrode. The crystalline layer has at least one channel, such as a line defect, extending from one surface of the crystalline layer to the other surface. Upon application of a voltage on the two electrodes, the active electrode provides metal ions that can migrate from the active electrode to the other electrode along the line defect, thereby forming a conductive filament. The switching cell can precisely locate the conductive filament within the line defect and increase the device-to-device switching uniformity.

A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines.

A resistive random access memory device is provided. The resistive random access memory device includes a first electrode, a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. One of the first electrode and the second electrode includes an ion supply layer providing two or more kinds of metal ions to the electrolyte layer. The two or more kinds of metal ions have different mobilities in the electrolyte layer. Two or more conductive bridges are generated by the two or more kinds of metal ions, respectively.

A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.

A semiconductor structure comprises a conductive bridge random access memory device and an access device connected in series with the conductive bridge random access memory device. The conductive bridge random access memory device and the access device are arranged in a vertical stack. The vertical stack has a sidewall profile that increases in width from a bottom surface of the vertical stack to a top surface of the vertical stack.

A memory device according to an embodiment of the present disclosure includes: a logic circuit in which a plurality of wiring layers including layers that are different in wiring pitches is stacked; and a memory element that is provided between the plurality of wiring layers.