Provided is a precursor of a current-perpendicular-to-plane giant magnetoresistive element having a laminated structure of ferromagnetic metal layer/nonmagnetic metal layer/ferromagnetic metal layer, the precursor having a nonmagnetic intermediate layer containing a non-magnetic metal and an oxide in a predetermined ratio such that the distribution thereof is nearly uniform at the atomic level. Also provided is a current-perpendicular-to-plane giant magnetoresistive element having a current-confinement structure (CCP) which has: a current confinement structure region made of a conductive alloy and obtained by heat-treating a laminated structure of a ferromagnetic metal layer and a nonmagnetic intermediate layer at a predetermined temperature; and a high-resistance metal alloy region containing an oxide and surrounding the current confinement structure region.

A spin-transfer torque (STT) magnetoresistive memory device includes a first electrode, a second electrode, and a magnetic tunnel junction located between the first electrode and the second electrode. The magnetic tunnel junction includes a reference layer having a fixed magnetization direction, a free layer stack, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer stack. The free layer stack has a total thickness of less than 2 nm, and contains in order, a proximal ferromagnetic layer located proximal to the nonmagnetic tunnel barrier layer, a first non-magnetic metal sub-monolayer, an intermediate ferromagnetic layer, a second non-magnetic metal sub-monolayer, and a distal ferromagnetic layer.

A magnetic tunnel junction (MTJ) element including a free layer, a reference layer; and a tunnel barrier layer between the free layer and the reference layer. The reference layer includes a first pinned layer, a second pinned layer, an anti-ferromagnetic coupling (AFC) spacer layer between the first pinned layer and the second pinned layer, a first spacer layer adjacent to the second pinned layer, a second spacer layer, a ferromagnetic layer sandwiched by the first spacer layer and the second spacer layer, a polarization enhancement layer adjacent to the second spacer layer.

A Magnetic Tunnel Junction (MTJ) device can include a reference magnetic layer having one or more trenches disposed therein. One or more sections of a tunnel barrier layer can be disposed on the walls of the one or more trenches. One or more sections of a free magnetic layer can be disposed on the one or more sections of the tunnel barrier layer in the one or more trenches. One or more sections of a conductive layer can be disposed on the one or more sections of the free magnetic layer in the one or more trenches. One or more insulator blocks can be disposed between corresponding sections of the tunnel barrier layer, corresponding sections of the free magnetic layer and corresponding sections of the conductive layer in the one or more trenches.

A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

A magnetic memory structure is provided. The magnetic memory structure includes a magnetic tunneling junction (MTJ) layer and a heavy-metal layer. The MTJ layer includes a pinned-layer, a barrier-layer formed under the pinned-layer and a free-layer formed under the barrier-layer. The heavy-metal layer is formed under the free-layer. The barrier-layer has a first upper surface, the pinned-layer has a lower surface, and area of the first upper surface is larger than area of the lower surface.

One illustrative MRAM cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the MTJ element includes a bottom insulation layer positioned above the bottom electrode, a top insulation layer positioned above the bottom electrode; and a first ferromagnetic material layer positioned between the bottom insulation layer and the top insulation layer.

Aspects of the present disclosure include magnetic sensor devices having a mixed oxide passivation layer. Magnetic sensor devices according to certain embodiments include a magnetic sensor element and a passivation layer having two or more of zirconium oxide, aluminum oxide and tantalum oxide. Also provided are magnetic sensor devices having an encapsulating passivation layer. Magnetic sensor devices according to certain embodiments include a substrate, a magnetic sensor element and a passivation layer that encapsulates the magnetic sensor element. Methods for making a magnetic sensor with a passivation layer are described. Methods and systems for detecting one or more analytes in a sample are also described. Aspects further include kits having one or more of the subject magnetic sensor devices and a magnetic label.

A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.