A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.

A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the same time providing a higher density of vertical transistor devices during the manufacturing process.

Disclosed embodiments include vacuum electronic devices and methods of fabricating a vacuum electronic device. In a non-limiting embodiment, a vacuum electronic device includes an electrode that defines discrete support structures therein. A first film layer is disposed on the electrode about a periphery of the electrode and on the support structures. A second film layer is disposed on the first film layer. The second film layer includes electrically conductive grid lines patterned therein that are supported by and suspended between the support structures.

A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

A vacuum micro-electronics device that utilizes fissile material capable of using the existing neutron leakage from the fuel assemblies of a nuclear reactor to produce thermal energy to power the heater/cathode element of the vacuum micro-electronics device and a self-powered detector emitter to produce the voltage/current necessary to power the anode/plate terminal of the vacuum micro-electronics device.

A horizontal vacuum channel transistor is provided. The horizontal transistor includes a substrate, horizontal emitter and collector electrodes formed in a layer of semiconductor material of the substrate, and a horizontal insulated gate located between the emitter and collector electrodes. The emitter electrode includes multiple horizontally-aligned emitter tips connected to a planar common portion, and the collector electrode includes a planar portion. The gate includes multiple horizontally-aligned gate apertures passing through the gate that each correspond to one of the emitter tips of the emitter electrode. The minimum distance between the emitter and collector electrodes is less than about 180 nm. Also provided are a vertical vacuum channel transistor having vertically-stacked emitter and collector electrodes, and methods for fabricating vacuum channel transistors.

A vacuum electron tube comprises at least one electron-emitting cathode and at least one anode arranged in a vacuum chamber, the cathode having a planar structure comprising a substrate comprising a conductive material, a plurality of nanotube or nanowire elements electrically insulated from the substrate, the longitudinal axis of the nanotube or nanowire elements substantially parallel to the plane of the substrate, and at least one first connector electrically linked to at least one nanotube or nanowire element so as to be able to apply a first electrical potential to the nanowire or nanotube element.

A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

Nanoscale field-emission devices are presented, wherein the devices include at least a pair of electrodes separated by a gap through which field emission of electrons from one electrode to the other occurs. The gap is dimensioned such that only a low voltage is required to induce field emission. As a result, the emitted electrons energy that is below the ionization potential of the gas or gasses that reside within the gap. In some embodiments, the gap is small enough that the distance between the electrodes is shorter than the mean-free path of electrons in air at atmospheric pressure. As a result, the field-emission devices do not require a vacuum environment for operation.

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.