A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.

A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.

Disclosed embodiments include vacuum electronic devices and methods of fabricating a vacuum electronic device. In a non-limiting embodiment, a vacuum electronic device includes an electrode that defines discrete support structures therein. A first film layer is disposed on the electrode about a periphery of the electrode and on the support structures. A second film layer is disposed on the first film layer. The second film layer includes electrically conductive grid lines patterned therein that are supported by and suspended between the support structures.

A chip scale encapsulated vacuum field emission device integrated circuit and method of fabrication therefor are disclosed. The vacuum field emission device is a monolithically fabricated triode vacuum field emission device, also known as a VACFET device. The VACFET device includes a substrate, a VACFET formed laterally on the substrate, and a containment shell that seals around a periphery of the VACFET and against the substrate. Preferably, the VACFET of the VACFET device includes an anode and a cathode formed on the substrate, a bottom gate and a top gate. The bottom gate is located between the anode and the cathode and the substrate, and the top gate is located above the anode and the cathode with respect to the substrate.

A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.

A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.

The present disclosure relates to methods of fabricating electronic devices or components thereof. The electronic devices can be vacuum electronic devices. The methods can include disposing a first material on or in a substrate. The methods can further include removing a portion of the first material to form one or more structure protruding from the substrate. The methods can further include disposing a second material onto the one or more structure of the first material, and then removing a portion of the second material to form one or more sidewall structures. A second portion of the one or more structures of the first material can also be removed to form a fabricated structure including the substrate and one or more sidewall structures protruding therefrom.

A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.

A carbon nanotube triode apparatus includes a plurality of Horizontally Aligned Single Wall Carbon Nano Tubes (HA-SWCNT) disposed on an electrically insulating thermally conductive substrate. A first contact is disposed on the substrate and electrically coupled to a first end of the HA-SWCNT. A second contact is disposed on the substrate and separated from a second end of the HA-SWCNT by a gap. A gate terminal is coincident with a plane of the substrate.

A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.