The invention discloses a method for cutting a substrate wafer from an indium phosphide crystal, and belongs to the field of semiconductor substrate preparation, comprises the following steps of: 1) orientating, cutting the head and the tail of a crystal bar, adjusting the orientation and trying to cut the crystal bar until a wafer with a required crystal orientation cut, wherein the cutting end face is an orientation end face; 2) multi-wire cutting, on a multi-wire cutting apparatus, dividing a crystal bar parallel to an orientation end face into wafers; 3) cleaning, cleaning the wafer until no residue and no dirt existing on the surface; 4) circle cutting, performing circle cutting on the wafer to cut the desired crystal orientation area. According to the technical scheme, for the indium phosphide crystal bar which is difficult to control in diameter and easy to twinning/ poly in the growth process, a barreling process which may grind and remove a large amount of InP materials is abandoned, the crystal bar is multi-wire cut into a wafer, and then the substrate wafer which is available in the crystal direction close to the standard size is cut from the wafer to the maximum extent, so that the wafer output can be greatly increased, and the material loss and the waste can be reduced.

A silicon carbide epitaxial substrate includes a silicon carbide substrate, a first silicon carbide epitaxial layer, and a second silicon carbide epitaxial layer. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first silicon carbide epitaxial layer is in contact with a whole of the first main surface. The second silicon carbide epitaxial layer is in contact with a whole of the second main surface. A carrier concentration of the silicon carbide substrate is higher than a carrier concentration of each of the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer.

An out-of-plane deformable semiconductor substrate includes a plurality of rigid portions having a first thickness and an out-of-plane deformable portion having a second thickness and connecting the plurality of rigid portions to each other. The second thickness is smaller than the first thickness. The out-of-plane deformable semiconductor substrate is monolithic.

Implementations of a packaging system may include a wafer; and a curvature adjustment structure coupled thereto where the curvature adjustment structure may be configured to alter a curvature of a largest planar surface of the wafer.

The present disclosure provides a method for wafer bonding, including providing a wafer, forming a sacrificial layer on a top surface of the first wafer, trimming an edge of the first wafer to obtain a first wafer area, cleaning the top surface of the first wafer, removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer having a second wafer area greater than the first wafer area.

In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.

The present invention provides an aluminum nitride wafer and a method for making the same. The method includes forming at least one alignment notch in or at least one flat alignment edge on a periphery of the aluminum nitride wafer. The alignment notch and the flat alignment edge can prevent the aluminum nitride wafer from being in a poor state during the semiconductor manufacturing process and makes it possible to position the aluminum nitride wafer precisely so that the fraction defective can be lowered. The aluminum nitride wafer of the present invention has advantages of effective insulation, efficient heat dissipation, and a high dielectric constant, and can be used in semiconductor manufacturing processes, electronic products, and semiconductor equipment.

A method for forming a through-substrate via structure includes providing a substrate and providing a conductive via structure adjacent to a first surface of the substrate. The method includes providing a recessed region on an opposite surface of the substrate towards the conductive via structure. The method includes providing an insulator in the recessed region and providing a conductive region extending along a first sidewall surface of the recessed region in the cross-sectional view. In some examples, the first conductive region is provided to be coupled to the conductive via structure and to be further along at least a portion of the opposite surface of the substrate outside of the recessed region. The method includes providing a protective structure within the recessed region over a first portion of the first conductive region but not over a second portion of the first conductive region that is outside of the recessed region. The method includes attaching a conductive bump to the second portion of the first conductive region.

A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.

A wafer polishing method includes moving a polishing pad to a standby position where a gap is defined between the upper surface of a wafer held on a holding unit and the lower surface of the polishing pad, lowering the polishing pad from the standby position by a preset distance at a preset speed, determining whether or not a load measured by a load sensor is greater than or equal to a preset threshold value in a rest condition of the polishing pad after lowering the polishing pad, repeatedly the lowering the polishing pad until it is determined that the load measured by the load sensor is greater than or equal to the threshold value, and polishing the wafer in the condition where a load falling in a predetermined load range including the threshold value.