An object of the present invention is to provide a treatment liquid for manufacturing a semiconductor and a pattern forming method, in which the formation of particles including metal atoms can be reduced and an excellent pattern can be formed. A treatment liquid for manufacturing a semiconductor according to an embodiment of the present invention includes: a quaternary ammonium compound represented by Formula (N); at least one additive selected from the group consisting of an anionic surfactant, a nonionic surfactant, a cationic surfactant, and a chelating agent; and water. The treatment liquid for manufacturing a semiconductor includes one kind or two or more kinds of metal atoms selected from the group consisting of Na, K, Ca, Fe, Cu, Mg, Mn, Li, Al, Cr, Ni, and Zn, and a total mass of the metal atoms is 1 mass ppt to 1 mass ppm with respect to the sum of a total mass of the additive and the total mass of the metal atoms.

Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

There is provided a new coating liquid for resist pattern coating. A coating liquid for resist pattern coating comprising a component A that is a polymer including at least one hydroxy group or carboxy group; a component B that is a sulfonic acid of A-SO.sub.3H (where A is a linear or branched alkyl group or fluorinated alkyl group having a carbon atom number of 1 to 16, an aromatic group having at least one of the alkyl group or the fluorinated alkyl group as a substituent, or a C.sub.4-16 alicyclic group optionally having a substituent); and a component C that is an organic solvent capable of dissolving the polymer and including ether or ketone compound of R.sup.1—O—R.sup.2 and/or R.sup.1—C(═O)—R.sup.2 (where R.sup.1 is a linear, branched, or cyclic alkyl group or fluorinated alkyl group having a carbon atom number of 3 to 16; and R.sup.2 is a linear, branched, or cyclic alkyl group or fluorinated alkyl group having a carbon atom number of 1 to 16), a method of forming a resist pattern using the coating liquid, and a method for forming a reverse pattern using the coating liquid.

According to the present disclosure, there are provided a surface treatment agent having the advantage that the raw material components can be dissolved in a short time during preparation of the surface treatment agent and capable of exerting a good water repellency imparting effect, and a method of manufacturing a surface-treated body with the use of the surface treatment agent. The surface treatment agent according to the present disclosure includes the following components: (I) at least one kind selected from the group consisting of silicon compounds represented by the following general formulas [1], [2] and [3]; (II) at least one kind selected from the group consisting of a nitrogen-containing heterocyclic compound represented by the following general formula [4], a nitrogen-containing heterocyclic compound represented by the following general formula [5], and imidazole; and (III) an organic solvent. ##STR00001##

One or more embodiments are directed to methods of removing a sacrificial layer from semiconductor wafers during wafer processing. In at least one embodiment, the sacrificial layer is removed from a wafer during an O.sub.2 plasma etch step. In one embodiment, the sacrificial layer is poly(p-phenylene-2, 6-benzobisoxazole) (PBO) or polyimide. The O.sub.2 plasma etch step causes a residue to form on the wafer. The residue is removed by immersing the wafer a solution that is a mixture of the tetramethylammonium hydroxide (TMAH) and water.

A liquid processing method for liquid-processing a substrate includes setting a substrate on a substrate holding device which rotates the substrate such that the substrate is held in horizontal position, supplying processing liquid to center portion of the substrate such that the center portion positioned center side with respect to peripheral portion of the substrate is liquid-processed, positioning a discharge port of a processing liquid nozzle toward downstream side in rotation direction such that the liquid is discharged to the peripheral portion obliquely to surface of the substrate and along tangential direction of the substrate while the substrate is rotated, and discharging gas from a gas nozzle perpendicularly to the surface of the substrate toward position that is adjacent to liquid landing position of the liquid on the surface of the substrate and is on the center side of the substrate, while the liquid is discharged to the peripheral portion.

The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

A method for manufacturing a bit line structure includes the following operations. A bit line conductive layer is formed on a surface of a semiconductor substrate, and the bit line conductive layer is partially located in a groove in the surface of the semiconductor substrate. A first protective layer is formed on surfaces of the bit line conductive layer and the semiconductor substrate. A first barrier layer is formed on a surface of the first protective layer. The surface of the first barrier layer is subjected with passivating treatment. A sacrificial layer is formed on the surface of the first barrier layer, and is provided with a filling part filled in the groove. A part, other than the filling part, of the sacrificial layer is cleaned and stripped.

A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.