A method and a device for prefixing substrates, whereby at least one substrate surface of the substrates is amorphized in at least one surface area, characterized in that the substrates are aligned and then make contact and are prefixed on the amorphized surface areas.

Disclosed herein are systems and methods for treating the surface of a microelectronic substrate, and in particular, relate to an apparatus and method for scanning the microelectronic substrate through a cryogenic fluid mixture used to treat an exposed surface of the microelectronic substrate. In particular, an improved nozzle design used to expand the fluid mixture is disclosed herein. In one embodiment, the nozzle design incorporates a two nozzle pieces are combined to form a single nozzle design, in which the two pieces are slight misaligned to form a unique orifice design. In another embodiment, two pieces are combined and aligned along a common axis of the fluid conduit. However, an offset piece is inserted between the two pieces and has a hole that misaligned from the flow conduits of the two other pieces.

Provided is a method for treating a substrate which removes particle within a concave portion on a substrate having a thin film on which a pattern having the concave portion on its upper surface is formed. The substrate treating method according the present invention comprises a penetration step for penetrating a treatment liquid containing supercritical organic chemical solution into the concave portion; and a heating step for heating the substrate after the penetration step.

A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.

A semiconductor device includes semiconductor nanostructures disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor nanostructures, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor nanostructures, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor nanostructures, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

A chuck table for supporting a wafer assembly during a cleaning process comprising an axis of rotation, a first surface including an opening configured to be in communication with a vacuum source, and a second surface opposing the first surface. The second surface includes a suction opening displaced radially from both the opening in the first surface and the axis, the suction opening being in communication with the opening in the first surface such that in use a suction force can be applied via the suction opening.

A method of controlling chemical concentration in electrolyte includes measuring a chemical concentration in an electrolyte, wherein the electrolyte is contained in a tank; and increasing a vapor flux through an exhaust pipe connected to the tank when the measured chemical concentration is lower than a control lower limit value.

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H.sub.3PO.sub.4 solution.

Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.