A semiconductor device includes a first semiconductor layer having a first surface and a second surface. A first metal film is disposed on the first surface. An outer portion of the first surface beyond an outer periphery of the first metal film is left uncovered by the first metal film. A semiconductor substrate has an inner region of a first thickness and a peripheral region of a second thickness, greater than the first thickness. A portion of the first semiconductor layer is between the inner region and the first metal layer. The peripheral region of the semiconductor substrate is below the outer portion of the first surface of the first semiconductor layer. A second metal film is below the inner region of the semiconductor substrate and adjacent to the peripheral region of the semiconductor substrate.

Double-patterning methods for build-up metallization features suitable for IC package assemblies. Double-patterned metallization features may, for example, achieve approximately twice the aspect ratio of single patterned metallization features for a given photolithography technology node. High aspect ratio metallization features may include a top feature portion that is over a bottom feature portion. The top and bottom portions each have a distinct sidewall slope indicative of their double-patterning. A hybrid plating mask may be employed during a metallization plating process. The hybrid mask may include multiple layers of photoresist to reach a desired mask thickness. Multiple exposures may be performed to incrementally image the hybrid plating mask, thereby maintaining better resolution for each exposure. In some exemplary embodiments, one layer of the hybrid plating mask has a negative photoresist composition into which features may be hardened through a first exposure, while another layer of the hybrid plating mask has a positive photoresist composition from which features may retained by protecting them from a second exposure.

The present disclosure advances the art by providing a method and system for forming electronic devices. In particular, and by example only, methods are described for forming devices for harvesting energy in the terahertz frequency range on flexible substrates, wherein the methods provide favorable accuracy in registration of the various device elements and facilitate low-cost R2R manufacturing.

The disclosed technique may be used to electrically and physically connect semiconductor wafers to allow high density interconnects and accommodate mismatched coefficients of thermal expansion materials by having room temperature hybridization as well as to remove the bow from wafers. The wafers may utilize a thick dielectric to remove the bow and create a planar surface. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together. The small size of the columns enables wafer or chip scale hybridization with a very high interconnect density, high reliability, and the ability to accommodate mismatches in the coefficients of thermal expansion of the constituent materials.

A line structure for fan-out circuit having a dense-line area and a fan-out area is provided. The line structure includes a plurality of dense lines arranged in the dense-line area parallel to a first direction, a plurality of pads disposed in the fan-out area, and a plurality of connecting lines arranged in the fan-out area parallel to a second direction. The connecting lines respectively connect one of the dense lines with one of the pads, wherein at least one of the connecting lines is a wavy line.

A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.

Included are forming, on a semiconductor substrate, an insulation film having an opening section where an opening is formed, forming a first resist on the insulation film while avoiding the opening section and the semiconductor substrate exposed via the opening section, forming a first metal on the opening section, the semiconductor substrate exposed via the opening section, and the first resist by a vapor deposition method or a sputtering method, removing, by a lift-off method, the first resist and the first metal on the first resist, forming, on the insulation film, a second resist allowing the first metal to be exposed, causing the first metal to grow a second metal by an electroless plating method, and removing the second resist, where these processings are included in the listed order.

A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.

A method for manufacturing a semiconductor device includes: supplying a resist to a first surface of a semiconductor element having a plurality of electrode pads to cover the electrode pad surfaces; opening the resist on the electrode pad surfaces to expose the electrode pad surfaces from the resist; curing the resist by applying light or heat to the resist; forming bump electrodes on the electrode pad surfaces by filling a plating solution into the openings of the resist; and peeling the resist from the first surface of the semiconductor element.

A method for forming a lift-off mask structure includes providing a substrate body, depositing a layer of bottom anti-reflective coating, BARC, over a surface of the substrate body, and depositing a layer of photosensitive resist over the BARC layer. The method further includes exposing the resist layer to electromagnetic radiation through a photomask, and forming the lift-off mask structure by applying a developer for selectively removing a portion of the BARC layer and of the resist layer such that an underlying portion of the surface of the substrate body is exposed.