A method of manufacturing a backplane for a display device includes forming an insulation layer on a substrate, forming a pad electrode layer on the insulation layer, forming a photoresist pattern on the pad electrode layer in the pad region, etching the pad electrode layer and a portion of the insulation layer by the photoresist pattern as an etch-stop layer so as to simultaneously form a pad electrode and a side protection layer, the side protection layer covering a sidewall of the pad electrode, and stripping the photoresist pattern.

A method of manufacturing a semiconductor element includes forming a first silicon oxide film on a semiconductor wafer under a first film forming condition; forming a second silicon oxide film on the first silicon oxide film under a second film forming condition, a density of the second silicon oxide film being lower than a density of the first silicon oxide film; coating, with a photoresist, a region including the second silicon oxide film; exposing the photoresist using a photomask having an aperture and being disposed such that at least a portion of an edge of the aperture is disposed on the second silicon oxide film; removing a portion of the photoresist to form a photoresist pattern that has an overhang shape in a cross-section of the photoresist pattern; forming an electrode film on a region including the photoresist pattern; and performing lift-off by removing the photoresist pattern.

A method of manufacturing a transistor comprising providing a substrate, a region of semiconductive material on the substrate, and a region of electrically conductive material on the region of semiconductive material; forming a covering of resist material over said regions; forming a depression in a surface of the covering of resist material that extends over a first portion of said region of conductive material, said first portion separating second and third portions of the conductive region; removing resist material located under said depression to form a window through said covering, exposing said first portion; removing said first portion to expose a connecting portion of the region of semiconductive material that connects the second and third portions; forming a layer of dielectric material over the exposed connecting portion; and forming a layer of electrically conductive material over said layer of dielectric material.

Deep reactive ion etching is essential for creating high aspect ratio micro-structures for microelectromechanical systems, sensors and actuators, and emerging flexible electronics. A novel hybrid dual soft/hard mask bilayer may be deposited during semiconductor manufacturing for deep reactive etches. Such a manufacturing process may include depositing a first mask material on a substrate; depositing a second mask material on the first mask material; depositing a third mask material on the second mask material; patterning the third mask material with a pattern corresponding to one or more trenches for transfer to the substrate; transferring the pattern from the third mask material to the second mask material; transferring the pattern from the second mask material to the first mask material; and/or transferring the pattern from the first mask material to the substrate.

A process of forming a field effect transistor is disclosed. The process includes steps of depositing a first silicon nitride (SiN) film on a semiconductor layer by a low pressure chemical vapor deposition (LPCVD) technique; depositing a second SiN film on the first SiN film by plasma assisted chemical vapor deposition (p-CVD) technique; preparing a photoresist mask on the second SiN film, the photoresist mask having an opening in a position corresponding to the gate electrode; dry-etching the second SiN film and the first SiN film continuously in a portion of the opening in the photoresist mask to form an opening in the first SiN film and an opening in the second SiN film, the openings in the first and second SiN films exposing the semiconductor layer; and filling at least the opening in the first SiN film by the gate electrode. A feature of the process is that the opening in the first SiN film has an inclined side against the semiconductor layer and gradually widens from the semiconductor layer.

A method for forming a semiconductor structure is provided. The method includes forming a first material and a second material on a semiconductor substrate. The first material is different from the second material. The method also includes heating the first material to a first temperature and the second material to a second temperature with a laser beam. The first temperature is different from the second temperature. The method also includes depositing a third material on the first material.

Methods for asymmetric deposition of a material on a structure formed on a substrate are provided herein. In some embodiments, a method for asymmetric deposition of a material includes forming a plasma from a process gas comprising ionized fluorocarbon (CxFy) particles, depositing an asymmetric fluorocarbon (CxFy) polymer coating on a first sidewall and a bottom portion of an opening formed in a first dielectric layer using angled CxFy ions, depositing a metal, metallic nitride, or metallic oxide on a second sidewall of the opening, and removing the CxFy polymer coating from the first sidewall and the bottom portion of the opening to leave an asymmetric deposition of the metal, metallic nitride, or metallic oxide on the structure.

A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.

A method of making nanoscale channels including: providing a substrate, locating a photoresist mask layer on the substrate, the thickness of the photoresist mask layer equals H; forming a patterned mask layer by exposing and developing the photoresist mask layer, the patterned mask layer includes a plurality of parallel and spaced stripe masks, the spacing between adjacent stripe masks equals L; depositing a first thin film layer on the substrate in a first direction, the thickness of the first thin film layer equals D, a first angle between the first direction and a direction in the thickness of the stripe masks equals .sub.1, .sub.1<tan.sup.1(L/H); depositing a second thin film layer on the substrate in a second direction, a second angle between the second direction and the direction in the thickness of the stripe masks equals .sub.2, .sub.2<tan.sup.1[L/(H+D)], 0<Htan.sub.1+(H+D)tan.sub.2L<10 nm.

A method of making thin film transistor including: forming a gate electrode, forming a gate insulating layer on the gate electrode; locating a semiconductor layer on the gate insulating layer; placing stripe-shaped masks on the semiconductor layer, wherein the thickness of the stripe-shaped masks is H, the spacing distance between the stripe-shaped masks is L; depositing a first conductive film layer along a first direction, the thickness of the first conductive film layer is D, a first angle between the first direction and a direction along the thickness of the stripe-shaped masks is .sub.1, .sub.1<tan.sup.1(L/H); depositing a second conductive film layer along a second direction, a second angle between the second direction and the direction along the thickness of the stripe-shaped masks is .sub.2, .sub.2<tan.sup.1[L/(H+D)], 0<Htan.sub.1+(H+D)tan.sub.2L<10 nm, the first conductive film layer forms a source electrode, the second conductive film layer forms a drain electrode.