A semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment.

An Inorganic Lift-Off-Profile-Process (referred to herein as ILOPP) is described wherein a portion of a surface inorganic oxide is etched from a substrate oxide surface and under a photoresist edge that supports a sacrificial metal layer. This oxide etched profile under the sacrificial photoresist/metal edge improves Lift-Off of the sacrificial metal layer and delivers smoother, improved metal edge definition in addition to an improved planer surface (flatness) as compared to known LOP technologies.

A method of making a thin film transistor, the method including: providing an insulating layer on a semiconductor substrate, forming a semiconductor layer on the insulating layer; locating a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, wherein the nanowire structure comprises a nanowire; forming an opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed in the opening; depositing a conductive film layer on the exposed surface of the semiconductor layer, wherein the conductive film layer defines a nano-scaled channel corresponding to the nanowire, and the conductive film layer is divided into two regions by the nano-scaled channel, one region is used as a source electrode, and the other region is used as a drain electrode; forming a gate electrode on the semiconductor substrate.

A method of making nano-scaled channel, the method including: locating a first photoresist layer, a nanowire structure, and a second photoresist layer on a surface of a substrate, and the nanowire structure being sandwiched between the first photoresist layer and the second photoresist layer, wherein the nanowire structure comprises an nanowire; forming an opening in the first photoresist layer and the second photoresist layer to expose a portion of the surface of the substrate to form an exposed surface, wherein a part of the nanowire is exposed and suspended in the opening, and both ends of the nanowire are sandwiched between the first photoresist layer and the second photoresist layer; and depositing a thin film layer on the exposed surface of the substrate using the a nanowire as a mask, wherein the thin film layer defines a nano-scaled channel corresponding to the at least one nanowire.

Methods and apparatus for asymmetric deposition of a material on a structure formed on a substrate are provided herein. In some embodiments, a method for asymmetric deposition of a material includes forming a plasma from a process gas comprising ionized fluorocarbon (CxFy) particles, depositing an asymmetric fluorocarbon (CxFy) polymer coating on a first sidewall and a bottom portion of an opening formed in a first dielectric layer using angled CxFy ions, depositing a metal, metallic nitride, or metallic oxide on a second sidewall of the opening, and removing the CxFy polymer coating from the first sidewall and the bottom portion of the opening to leave an asymmetric deposition of the metal, metallic nitride, or metallic oxide on the structure.

A semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment.

A method of enhancing generation efficiency of patterned optical coating is disclosed. When an exposure and development process is performed after a photoresist process on the silicon wafer, a dummy pattern is formed on a scribe line around a chip as a sacrificial layer. After an optical coating process is completed, the dummy pattern from the photoresist to be removed can be selected as the starting point of a photoresist lift-off process, such that the photoresist removal can be more efficient and accurate, and the generation efficiency of patterned optical coating is enhanced.

A semiconductor device and a process of forming the semiconductor device are disclosed. The semiconductor device type of a high electron mobility transistor (HEMT) has double SiN films on a semiconductor layer, where the first SiN film is formed by the lower pressure chemical vapor deposition (LPCVD) technique, while, the second SiN film is deposited by the plasma assisted CVD (p-CVD) technique. Moreover, the gate electrode has an arrangement of double metals, one of which contains nickel (Ni) as a Schottky metal, while the other is free from Ni and covers the former metal. A feature of the invention is that the first metal is in contact with the semiconductor layer but apart from the second SiN film.

A method of manufacturing a semiconductor element includes forming a first silicon oxide film on a semiconductor wafer under a first film forming condition; forming a second silicon oxide film on the first silicon oxide film under a second film forming condition, a density of the second silicon oxide film being lower than a density of the first silicon oxide film; coating, with a photoresist, a region including the second silicon oxide film; exposing the photoresist using a photomask having an aperture and being disposed such that at least a portion of an edge of the aperture is disposed on the second silicon oxide film; removing a portion of the photoresist to form a photoresist pattern that has an overhang shape in a cross-section of the photoresist pattern; forming an electrode film on a region including the photoresist pattern; and performing lift-off by removing the photoresist pattern.

A method of manufacturing an electrode structure for a device, such as a GaN or AlGaN device is described. In one example, the method includes providing a substrate (212) of GaN or AlGaN with a surface region of the GaN or AlGaN exposed through an opening (216) in a layer of silicon nitride (214) formed on the substrate. The method further includes depositing layers of W (222), in one example, or Ni (220) and W (222), in another example, on the substrate and the layer of silicon nitride using reactive evaporation and photoresist layers (230) having an undercut profile for liftoff. The method further includes removing the photoresist layers having the undercut profile, and depositing layers of WN (224) and Al over the underlying layers of W or Ni and W by sputtering.