The invention relates to a method for forming flip chip bumps using electroplating. The method allows the formation of flip chip bumps in a way that is compatible with already-formed sensitive electronic components, such as Josephson junctions, which may be used in quantum processing units. The invention also relates to a product and a flip chip package in which flip chip bumps are formed with the disclosed method.

A nitride semiconductor device is disclosed. The semiconductor device is formed by a process that first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film.

A method for depositing, patterning and removing a layer of aluminum oxide as a masking material layer for performing a deep, high-aspect ratio etches into a substrate. The method comprising deposing a photoresist onto the substrate, performing lithography processing on the photoresist, developing the photoresist to pattern the photoresist into a mask design, depositing a thin-film layer of aluminum oxide; immersing the substrate into a solution to lift-off the aluminum oxide in regions where the aluminum oxide is deposited on top of the photoresist thereby leaving the patterned aluminum oxide layer on the substrate where no photoresist was present, performing deep reactive ion etching on the substrate wherein the hard masking material layer composed of aluminum oxide functions as a protective masking layer on the substrate to prevent etching from occurring where the aluminum oxide is present, and removing the aluminum oxide masking layer by immersion in a solution.

A resist underlayer film forming composition which has high storage stability, has a low film curing start temperature, can cause the generation of a sublimated product in a reduced amount, and enables the formation of a film that is rarely eluted into a photoresist solvent; a method for forming a resist pattern using the resist underlayer film forming composition; and a method for manufacturing a semiconductor device. The resist underlayer film forming composition includes a crosslinkable resin, a crosslinking agent, a crosslinking catalyst represented by formula (I) and a solvent. (A-SO.sub.3).sup.−(BH).sup.+[wherein A represents a linear, branched or cyclic saturated or unsaturated aliphatic hydrocarbon group which may be substituted, an aryl group which may be substituted by a group other than a hydroxy group, or a heteroaryl group which may be substituted; and B represents a base having a pKa value of 6.5 to 9.5.]

A method for manufacturing semiconductor elements by a metal lift-off process and a semiconductor element manufactured thereby, include steps of photoresist-coating, exposing, developing, metal-coating, and lift-off. A photoresist layer can be removed with a photoresist stripper. Meanwhile, the metal on the top of the photoresist layer can also be removed when the photoresist layer is removed. The circuit layout required for the semiconductor element can thus be completed without an etching process. In addition, by setting the process parameters, the contour of the photoresist layer can present a certain angle, so that the metal on the surface of the photoresist layer can be completely removed, which saves costs and improves competitiveness.

An organic film forming composition, containing: a material shown by formula (I) and/or (II); and an organic solvent, where R.sub.1 and R.sub.4 each represent a hydrogen atom, an allyl or propargyl group, R.sub.2 and R.sub.5 each represent a substituent, R.sub.3 and R.sub.6 represents a hydrogen atom, an alkyl group having 1 to 4 carbon atoms, an alkynyl group having 2 to 4 carbon atoms, or an alkenyl group having 2 to 4 carbon atoms. “m” and “i” represent 0 or 1, “k” and “q” represent an integer of 0 to 2, “n” represent 1 or 2, “h”, and “j” represent an integer of 0 to 2 and satisfy the relationship 1≤h+j≤4, and “1” and “r” represent 0 or 1. W represents a single bond or divalent group shown by formulae (3). Each V independently represents a hydrogen atom or linking moiety.

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A tunneling device includes a first semiconductor portion disposed on a first oxide substrate, a second semiconductor portion disposed on the first semiconductor portion, and an intermediate layer disposed between the first semiconductor portion and second semiconductor portion. The intermediate layer is a natural oxide film obtained by naturally oxidizing one surface of the second semiconductor portion for a predetermined time.

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

A touch panel and a method of manufacturing the touch panel are provided. The touch panel includes a substrate comprising a wiring area and a sensor area, a sensing pattern located on a surface of the substrate in the sensor area, and a wiring line located on the surface of the substrate in the wiring area and electrically connected to the sensing pattern. The sensing pattern includes a plurality of first fine metal lines arranged irregularly in a mesh, and a first photosensitive layer pattern residue located between at least two of the first fine metal lines.

A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.