A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.

A method of forming sub-resolution features that includes: exposing a photoresist layer formed over a substrate to a first ultraviolet light (UV) radiation having a first wavelength of 365 nm or longer through a mask configured to form features at a first critical dimension, the photoresist layer including first portions exposed to the first UV radiation and second portions unexposed to the first UV radiation after exposing with the first UV radiation; exposing the first portions and the second portions to a second UV radiation; and developing the photoresist layer after exposing the photoresist layer to the second UV radiation to form the sub-resolution features having a second critical dimension less than the first critical dimension.

The disclosure relates to a sequential infiltration synthesis apparatus comprising: a reaction chamber constructed and arranged to accommodate at least one substrate; a first precursor flow path to provide the first precursor to the reaction chamber when a first flow controller is activated; a second precursor flow path to provide a second precursor to the reaction chamber when a second flow controller is activated; a removal flow path to allow removal of gas from the reaction chamber; a removal flow controller to create a gas flow in the reaction chamber to the removal flow path when the removal flow controller is activated; and, a sequence controller operably connected to the first, second and removal flow controllers and the sequence controller being programmed to enable infiltration of an infiltrateable material provided on the substrate in the reaction chamber. The apparatus may be provided with a heating system.

An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.

The present disclosure provides a method of heating a spin on coating (SOC) film on a wafer. The method includes actions S401 to S405. In action S401, a heating apparatus is provided. The heating apparatus includes a bake plate and an electromagnetic wave generator. In action S402, the bake plate is heated by a heating unit disposed in the bake plate. In action S403, the wafer is placed on the bake plate of the heating apparatus. In action S404, the electromagnetic wave generator generates an electromagnetic wave to heat the SOC film. The electromagnetic wave generated by the electromagnetic wave generator has a frequency within a range of 1 THz to 100 THz. In action S405, the wafer is removed from the bake plate of the heating apparatus.

An imprinting platform including a noble metal catalyst, a semiconductor substrate, and a pre-patterned polymer stamp, where the catalyst is attached to the stamp, and related methods and articles.

A method of fabricating a semiconductor device is disclosed. The method may include forming an etch-target layer, a mask layer, a blocking layer, and a photoresist layer, which are sequentially stacked on a substrate; forming a photoresist pattern, the forming the photoresist pattern including irradiating the photoresist layer with extreme ultraviolet (EUV) light; forming a mask layer, the forming the mask layer including etching the mask layer using the photoresist pattern as an etch mask; and forming a target pattern, the forming the target pattern including etching the etch-target layer using the mask pattern as an etch mask. The photoresist layer may include an organic metal oxide. The blocking layer may be a non-polar layer and may limit and/or prevent a metallic element in the photoresist layer from infiltrating into the mask layer.

A manufacturing method of a semiconductor structure includes at least the following steps. A patterned mask layer with a first opening is formed on a dielectric layer overlying a semiconductor substrate. A portion of the dielectric layer accessibly exposed by the first opening of the patterned mask layer is removed to form a second opening. A first protective film is formed on inner sidewalls of the dielectric layer and the patterned mask layer, where the second opening and the first protective film are formed at the same step. A second protective film is formed on the first protective film to form a protective structure covering the inner sidewalls. A portion of the semiconductor substrate accessibly exposed by the second opening is removed to form a via hole including an undercut underlying the protective structure. The via hole is trimmed and a through substrate via is formed in the via hole.

The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.

An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.