A process for depositing doped aluminum nitride (doped AlN) is disclosed. The process comprises subjecting a substrate to temporally separated exposures to an aluminum precursor and a nitrogen precursor to form an aluminum and nitrogen-containing compound on the substrate. The aluminum and nitrogen-containing compound is subsequently exposed to a dopant precursor to form doped AlN. The temporally separated exposures to an aluminum precursor and a nitrogen precursor, and the subsequent exposure to a dopant precursor together constitute a doped AlN deposition cycle. A plurality of doped AlN deposition cycles may be performed to deposit a doped AlN film of a desired thickness. The dopant content of the doped AlN can be tuned by performing a particular ratio of 1) separated exposures to an aluminum precursor and a nitrogen precursor, to 2) subsequent exposures to the dopant. The deposition may be performed in a batch process chamber, which may accommodate batches of 25 or more substrates. The deposition may be performed without exposure to plasma.

A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming an energy-sensitive layer over the target layer. The method also includes performing a first energy treating process to form a first treated portion in the energy-sensitive layer, and performing a second energy treating process to form a second treated portion in the energy-sensitive layer. The method further includes removing the first treated portion and the second treated portion to form a first opening and a second opening in the energy-sensitive layer, and transferring the first opening and the second opening into the target layer.

A finFET device and a method of forming are provided. The method includes forming a first dielectric layer over a transistor. The method also includes forming a second dielectric layer over the first dielectric layer. The method also includes forming a first opening in the second dielectric layer to expose at least a portion of a gate electrode of the transistor. The method also includes forming a second opening in the first dielectric layer to expose at least a portion of a source/drain region of the transistor. The second opening is connected to the first opening, and the first opening is formed before the second opening. The method also includes forming an electrical connector in the first opening and the second opening.

In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

A vertical memory device, including: a substrate including a cell array region and an extension region; gate electrodes stacked on each other with a plurality of levels, wherein each of the gate electrodes includes a pad, and wherein the pads disposed on the gate electrodes form at least one staircase structure on the extension region of the substrate; a channel extending in a first direction on the cell array region of the substrate through at least one of the gate electrodes; and dummy gate electrode groups disposed on the extension region of the substrate, wherein the dummy gate electrode groups includes dummy gate electrodes, wherein each of the dummy gate electrodes are spaced apart from a corresponding gate electrode among the gate electrodes stacked at a same level, wherein the dummy gate electrode groups are spaced apart from each other in a second direction.

Disclosed is a plasma processing method for processing a workpiece that includes: a silicon-containing etching target layer, an organic film provided on the etching target layer, an antireflective film provided on the organic layer, and a first mask provided on the antireflective layer, using a plasma processing apparatus having a processing container. The plasma processing method includes: etching the antireflective film using plasma generated in the processing container and the first mask to form a second mask from the antireflective film; etching the organic film using plasma generated in the processing container and the second mask to form a third mask from the organic film; generating plasma of a mixed gas including the first gas and the second gas in the processing container; and etching the etching target layer using plasma generated in the processing container and the third mask.

A heat treatment apparatus includes: a stage on which a substrate is placed and heated, the substrate including an exposed resist film formed on a surface of the substrate, and the exposed resist film exhibiting a change in solubility of an exposed portion or an unexposed portion in a liquid developer by reacting with water and being heated; a lifting mechanism configured to relatively raise and lower the substrate between a first position at which the substrate is placed on the stage and a second position which is spaced apart from the stage; and a gas supply configured to supply a first gas to the substrate located at the second position before moving to the first position, the first gas having a humidity higher than that of an atmosphere in which the stage is provided.

A method includes patterning a resist layer formed over a substrate, resulting in a resist pattern; and transferring the resist pattern to an anti-reflection coating (ARC) layer formed under the resist layer and over the substrate, resulting in a patterned ARC layer. The method further includes treating the patterned ARC layer with an ion beam, resulting in a treated patterned ARC layer, wherein the ion beam is generated with a first gas and is directed towards the patterned ARC layer at a tilt angle at least 10 degrees. The method further includes etching the substrate with the treated patterned ARC layer as an etch mask.

A method of descumming a dielectric layer is provided. In an embodiment the dielectric layer is deposited over a substrate, and a photoresist is applied, exposed, and developed after the photoresist has been applied. Once the pattern of the photoresist is transferred to the underlying dielectric layer, a descumming process is performed, wherein the descumming process utilizes a mixture of a carbon-containing precursor, a descumming precursor, and a carrier gas. The mixture is ignited into a treatment plasma, and the treatment plasma is applied to the dielectric layer in order to descum the dielectric layer.

The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.