A method for fabricating high-resolution features in a deep recess includes etching a cavity in a substrate, fabricating at least one focusing pattern on a bottom of the cavity, wherein fabricating the focusing pattern comprises coating a first photoresist on the bottom of the cavity, patterning the first photoresist to define a focusing etch area using contact lithography, and etching the focusing etch area, coating a second photoresist on the bottom of the cavity, using the focusing pattern to focus a high resolution lithography tool at the bottom of the cavity to pattern the second photoresist to define a microfabrication feature area; and forming a microfabrication feature in the microfabrication feature area.

According to one embodiment, an adjusting unit adjusts a refracting angle of incident light with respect to a substrate, a detector detects reflected light from the substrate, and a calculating unit calculates positional deviation of the pattern based on patterns respectively reflected in reflected lights obtained from the incident light generating N number of refracting angles with respect to the substrate, where N is an integer of two or greater.

Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness.

Facilitating throughput in nanoimprint lithography processes by using an imprint resist including fluorinated components and a substrate treated with a pretreatment composition to promote spreading of an imprint resist on the substrate. The interfacial surface energy between the pretreatment composition and air exceeds the interfacial surface energy between the imprint resist and air by at least 1 mN/m, and the contact angle of the imprint resist on the surface of the nanoimprint lithography template is less than 15°.

A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.

According to one embodiment, a polymer material is disclosed. The polymer material contains a polymer. The polymer contains a first monomer unit having a lone pair and an aromatic ring at a side chain, and a second monomer unit including a crosslinking group at a terminal of the side chain, with its molar ratio of 0.5 mol % to 10 mol % to all monomer units in the polymer. The polymer material can be used for manufacturing a composite film as a mask pattern for processing a target film on a substrate. The composite film can be formed by a process including, forming an organic film on the target film with the polymer material, patterning the organic film, and forming the composite film by impregnating a metal compound into the patterned organic film.

A chemical sensor is described having a substrate comprising a plurality of nanoribbons of an active layered nanomaterial, and a substance detection component for measuring a change in electrical or physical properties of at least a portion of the plurality of nanoribbons when in contact with a substance.

A high-temperature-stable spin-on-carbon (“SOC”) material that fills topography features on a substrate while planarizing the surface in a one-step, thin layer coating process is provided. The material comprises low molecular weight polyimides or diimides that are pre-imidized in solution rather than on the wafer. The SOC layers can survive harsh CVD conditions and are also SC1 resistant, especially on TiN and SiOx surfaces.

This application relates to a semiconductor structure processing method, including: providing a semiconductor layer including a pattern, where a trench is located amongst the pattern; cleaning the pattern using a rinse liquid, where the rinse liquid fills the trench after the cleaning; forming a flexible layer, where the flexible layer displaces the rinse liquid and fills the trench, and covers a surface of the semiconductor layer; and hardening the flexible layer and subsequently removing the flexible layer.

A semiconductor structure includes a substrate, an isolation structure formed in the substrate, and a word line including a first convex portion and a second convex portion. The first convex portion and the second convex portion are located in the isolation structure, and a depth of the first convex portion is greater than a depth of the second convex portion.