A method of manufacturing a semiconductor device, including forming an etching target film on a substrate; forming an anti-reflection film on the etching target film; forming a photoresist film on the anti-reflection film; exposing the photoresist film; performing heat treatment on the anti-reflection film and the photoresist film to form a covalent bond between the anti-reflection film and the photoresist film; and developing the photoresist film.

A via opening is provided in an interconnect dielectric material. Prior to line opening formation, a continuous layer of a sacrificial material is formed lining the entirety of the via opening. An organic planarization layer (OPL) and a photoresist that contains a line pattern are formed above the interconnect dielectric material. The line pattern is then transferred into an upper portion of the interconnect dielectric material, while maintaining a portion of the OPL and a portion of the continuous layer of sacrificial material within a lower portion of the via opening. The remaining portions of the OPL and the sacrificial material are then removed from the bottom portion of the via opening. A combined via opening/line opening is provided in which the via opening has a well controlled profile/geometry. An interconnect metal or metal alloy can then be formed into the combined via opening/line opening.

Disclosed is a method for manufacturing a semiconductor device. The method includes: a first pattern forming step of forming, on a pattern forming target film, a first film that is patterned to have a first pattern that includes lines which are aligned with each other with spaces of a predetermined interval being interposed therebetween, and include a portion separated by using a first cut mask; a step of forming a second film to cover a surface of the first film; and a second pattern forming step of forming a pattern forming target film that is patterned to have a second pattern, by separating a portion of the space of the first step using a second cut mask. The first and second cut mask includes a plurality of openings or light shielding portions that have equal shapes, respectively.

An apparatus includes: measurement flow passage portions as part of a respective plurality of supply paths of fluids to be supplied to a substrate, the measurement flow passage portions constituting measurement regions for measurement of foreign matter in the fluids, and being disposed so as to form a row with each other; a light irradiating unit configured to form an optical path in one of the flow passage portions, the light irradiating unit being shared by the plurality of flow passage portions; a moving mechanism configured to move the light irradiating unit relatively along a direction of arrangement of the flow passage portions to form the optical path within the flow passage portion selected among the plurality of flow passage portions; a light receiving unit including a light receiving element, the light receiving element receiving light transmitted by the flow passage portion; and a detecting unit configured to detect foreign matter in the fluid on a basis of a signal output from the light receiving element. Consequently, the number of necessary light irradiating units can be reduced, and the apparatus can be miniaturized.

Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

Under one aspect, a power Schottky diode includes a cathode; a semiconductor disposed over the cathode, the semiconductor including at least a first region and a second region, the second region defining a guard ring; an anode disposed over the first region and at least a portion of the guard ring, the anode including a metal, a junction between the anode and the first region defining a Schottky barrier; and an oxide disposed over the guard ring. Additionally, the power Schottky diode can include a resistive material disposed over at least a portion of the guard ring and at least a portion of the oxide. The resistive material can inhibit a flow of holes from the guard ring to the anode following a heavy ion strike to the guard ring. The anode further can be disposed over at least a portion of, or the entirety of, the resistive material.

An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

A method of treating resist features comprises positioning, in a process chamber, a substrate having a set of patterned resist features on a first side of the substrate and generating a plasma in the process chamber having a plasma sheath adjacent to the first side of the substrate. The method may further comprise modifying a shape of a boundary between the plasma and the plasma sheath with a plasma sheath modifier so that a portion of the shape of the boundary is not parallel to a plane defined by a front surface of the substrate facing the plasma, wherein ions from the plasma impinge on the patterned resist features over a wide angular range during a first exposure.

A method includes forming a first insulating layer over a substrate, the first insulating layer having a non-planar top surface, the first insulating layer having a first etch rate. A second insulating layer is formed over the first insulating layer, the second insulating layer having a non-planar top surface, the second insulating layer having a second etch rate, the second etch rate being greater than the first etch rate. The second insulating layer is polished, the polishing partially removing the second insulating layer. The first insulating layer and the second insulating layer are non-selectively recessed.

At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.