H01L21/0331

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
20170271170 · 2017-09-21 ·

According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.

GATE METAL FORMATION ON GALLIUM NITRIDE OR ALUMINUM GALLIUM NITRIDE

A method of manufacturing an electrode structure for a device, such as a GaN or AlGaN device is described. In one example, the method includes providing a substrate (212) of GaN or AlGaN with a surface region of the GaN or AlGaN exposed through an opening (216) in a layer of silicon nitride (214) formed on the substrate. The method further includes depositing layers of W (222), in one example, or Ni (220) and W (222), in another example, on the substrate and the layer of silicon nitride using reactive evaporation and photoresist layers (230) having an undercut profile for liftoff. The method further includes removing the photoresist layers having the undercut profile, and depositing layers of WN (224) and Al over the underlying layers of W or Ni and W by sputtering.

Semiconductor wafer and method for manufacturing semiconductor wafer thereof

Provided is a method for manufacturing a semiconductor wafer and a semiconductor wafer. The method includes: disposing a sacrificial layer on a first surface and a second surface of a patterned substrate, the patterned substrate comprising the first surface and the second surface having different normal directions; exposing the first surface by removing the first portion of the sacrificial layer disposed on the first surface; growing an original nitride buffer layer on the first surface and the second portion of the sacrificial layer; partially lifting off the second portion of the sacrificial layer disposed on the second surface such that at least one sub-portion of the second portion of the sacrificial layer remains on the second surface of the patterned substrate; and growing an epitaxial layer on the original nitride buffer layer, where a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate.

LARGE AREA METROLOGY AND PROCESS CONTROL FOR ANISOTROPIC CHEMICAL ETCHING

Various embodiments of the present technology generally relate to semiconductor device architectures and manufacturing techniques. More specifically, some embodiments of the present technology relate to large area metrology and process control for anisotropic chemical etching. Catalyst influenced chemical etching (CICE) can be used to create high aspect ratio semiconductor structures with dimensions in the nanometer to millimeter scale with anisotropic and smooth sidewalls. However, all aspects of the CICE process must be compatible with the equipment used in semiconductor fabrication facilities today, and they must be scalable to enable wafer scale processing with high yield and reliability. This invention relates to metrology and control of etch and CMOS compatible methods of patterning the catalyst and removing it without damaging the etched structures.

ETCHING PROTECTION LAYER STRUCTURE OF METAL SEMICONDUCTOR JUNCTION AND MANUFACTURING METHOD THEREOF
20220005701 · 2022-01-06 ·

An etching protection layer structure of a metal semiconductor junction includes a semiconductor substrate and a metal etching protection layer. The semiconductor substrate has a metal semiconductor contact layer. The metal etching protection layer is disposed on the metal semiconductor contact layer, and serves as an etching mask for the ridge structure of laser device during the inductively coupled plasma reactive ion etching (ICP-RIE) process. The disclosure is not necessary to remove the metal etching protection layer after completing the etching process.

SEMICONDUCTOR DEVICE AND METHOD
20210343529 · 2021-11-04 ·

A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

Process of forming nitride semiconductor device

A process of forming a nitride semiconductor device is disclosed. The process includes steps of: (a) forming insulating films on a semiconductor stack, where the insulating films include a first silicon nitride (SiN) film, a silicon oxide (SiO.sub.2) film, and a second SiN film; (b) forming an opening in the insulating films; (c) widening the opening in the SiO.sub.2 film; (d) forming a recess in the semiconductor stack using the insulating films as a mask; (e) growing a doped region within the recess and simultaneously depositing the nitride semiconductor material constituting the doped region on the second SiN film; and (f) removing the nitride semiconductor material deposited on the second SiN film and the second SiN film by removing the SiO.sub.2 film.

Thin film transistor, manufacturing method therefor, array substrate and display panel

A thin film transistor is provided and includes an active layer, a source electrode, a drain electrode, a gate electrode and a gate electrode insulating layer, the active layer includes a source electrode region, a drain electrode region and a channel region, the source electrode region and the drain electrode region include a first metal material, and the channel region includes a semiconductor material made from oxidation of the first metal material.

Semiconductor device and method

A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

MOLECULAR LAYER ETCHING

A method of etching an organic or hybrid inorganic/organic material. The method etches molecular layer deposition coatings. An etching cycle comprises a first half reaction exposing the coating to a precursor. A second half reaction exposes a second precursor, removing or etching a portion of the coating.