A thin film transistor is provided and includes an active layer, a source electrode, a drain electrode, a gate electrode and a gate electrode insulating layer, the active layer includes a source electrode region, a drain electrode region and a channel region, the source electrode region and the drain electrode region include a first metal material, and the channel region includes a semiconductor material made from oxidation of the first metal material.

A method is provided. A sacrificial layer is formed over a semiconductor substrate. An etching process is performed to form an opening in the sacrificial layer. The etching process includes a first cycle and a second cycle performed after the first cycle, and each of the first cycle and the second cycle includes applying a passivation gas and an etchant gas over the sacrificial layer, and performing an ionized gas bombardment on the sacrificial layer after applying the passivation gas and the etchant gas over the sacrificial layer. The passivation gas is applied at a first flow rate in the first cycle and is applied at a second flow rate in the second cycle, and the first flow rate is higher than the second flow rate.

A process of forming a nitride semiconductor device is disclosed. The process includes s steps of: (a) forming insulating films on a semiconductor stack, where the insulating films include a first silicon nitride (SiN) film, a silicon oxide (SiO.sub.2) film, and a second SiN film; (b) forming an opening in the insulating films; (c) widening the opening in the SiO.sub.2 film; (d) forming a recess in the semiconductor stack using the insulating films as a mask; (e) growing a doped region selectively within the recess simultaneously depositing the nitride semiconductor material constituting the doped region on the second SiN film; and (f) removing the nitride semiconductor material deposited on the second SiN film by removing the SiO.sub.2 film and the second SiN film.

A method of manufacturing an electrical device, comprising: forming a patterned inorganic liftoff layer to expose a target electrode site on a softening polymer layer, depositing an electrode layer on the inorganic liftoff layer and on the exposed target electrode site, and removing the inorganic liftoff layer by a horizontal liftoff etch to leave the electrode layer on the exposed target electrode site.

In accordance with at least one embodiment of the disclosure, a method of patterning platinum on a substrate is disclosed. In an embodiment, an adhesive layer is deposited over the substrate, a sacrificial layer is deposited over the adhesive layer, and a patterned photoresist layer is formed over the sacrificial layer. Then, the sacrificial layer is patterned utilizing the photoresist layer as a mask such that at least a portion of the adhesive layer is exposed. Subsequently, the top and sidewall surfaces of the patterned sacrificial layer and the first portion of the adhesive layer are covered by a platinum layer. Finally, the sacrificial layer and a portion of the platinum layer covering the top and sidewall surfaces of the sacrificial layer are etched, thereby leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate.

The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

Electrode structures and methods of manufacturing electrode structures for devices are described. An example electrode structure includes a gate metal formation including a nitride layer with an opening that exposes a surface region of a substrate, a gate metal layer on the surface region of the substrate, a barrier metal layer on the gate metal layer and on at least a portion of a step around the opening in the nitride layer, and a conductive metal layer on the barrier metal layer. The gate metal layer is on the surface region of the substrate and on at least another portion of the step around the opening in the nitride layer in one example. The gate metal layer includes first and second gate metal layers in one example, such as nickel and tungsten.

An array substrate and a manufacturing method. The method includes: patterning the first metal layer through a first mask to form a gate electrode and a first conductive layer which are disposed at an interval; patterning the semiconductor and the gate insulation layer through a second mask to form a through hole for revealing the first conductive layer; patterning the semiconductor layer through the gate electrode and the first conductive layer to form a first channel and a second channel region which are disposed at an interval; patterning the second metal layer through a third mask to form a source electrode, a drain electrode and a second conductive layer which are disposed at intervals; wherein, the second conductive layer is contacted with the first conductive layer through the through hole. Accordingly, the gate insulation and the semiconductor layer are patterned through one mask to reduce the production cost.

The present invention provides a resist multilayer film-attached substrate, including a substrate and a resist multilayer film formed on the substrate, in which the resist multilayer film has an organic resist underlayer film difficultly soluble in ammonia hydrogen peroxide water, an organic film soluble in ammonia hydrogen peroxide water, a silicon-containing resist middle layer film, and a resist upper layer film laminated on the substrate in the stated order. There can be provided a resist multilayer film-attached substrate that enables a silicon residue modified by dry etching to be easily removed in a wet manner with a removing liquid harmless to a semiconductor apparatus substrate and an organic resist underlayer film required in the patterning process, for example, an ammonia aqueous solution containing hydrogen peroxide called SC1, which is commonly used in the semiconductor manufacturing process.