A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH.sub.3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH.sub.3 bonds less than the first content of Si—CH.sub.3 bonds.

A silicon-containing composition includes: a first polysiloxane; a second polysiloxane different from the first polysiloxane; and a solvent. The first polysiloxane includes a group which includes at least one selected from the group consisting of an ester bond, a carbonate structure, and a cyano group. The second polysiloxane includes a substituted or unsubstituted hydrocarbon group having 1 to 20 carbon atoms.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

Methods of forming structures including a photoresist underlayer and an adhesion layer and structures including the photoresist underlayer and adhesion layer are disclosed. Exemplary methods include forming the photoresist underlayer and forming an adhesion layer using a cyclical deposition process. The adhesion layer can be formed within the same reaction chamber used to form the photoresist underlayer.

A method of semiconductor manufacturing using a hard mask, a method for forming a pattern, and a semiconductor structure are provided. The method includes: providing a supporting base comprising a patterned sacrificial layer; forming a first protective layer covering sidewalls of the sacrificial layer; forming a first mask layer covering sidewalls of the first protective layer; removing the sacrificial layer; and removing the first protective layer from the sidewalls of the first mask layer.

A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

A method for forming a semiconductor device is provided. The method for forming a semiconductor device is provided. The method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.

Provided is a semiconductor device. The semiconductor device includes a wafer; an etch stop layer on the wafer; a lower mold layer on the etch stop layer; an intermediate supporter layer on the lower mold layer; an upper mold layer on the intermediate supporter layer; an upper supporter layer on the upper mold layer; and a hard mask structure on the upper supporter layer, wherein the hard mask structure includes a first hard mask layer on the upper supporter layer and a second hard mask layer on the first hard mask layer, one of the first hard mask layer and the second hard mask layer includes a first organic layer including a SOH containing C, H, O, and N, and the other one of the first hard mask layer and the second hard mask layer includes a second organic layer including an SOH containing C, H, and O.

Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The method includes: providing a base, at least one shallow trench isolating structure being formed in the base and several active regions arranged at an interval being isolated by the shallow trench isolating structure in the base; forming a first trench in the base, a part of the active regions being exposed in the first trench; forming a first conducting structure in the first trench; forming a first dielectric layer on the base; forming a second trench in the first dielectric layer, the first conducting structure being exposed in the second trench and a width of a top of the second trench being greater than a width of a top of the first trench; and forming a second conducting structure in the second trench.