A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

Provide is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a post spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the exposing the patterned structure, the atomic layer conformal deposition process, and the post spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objectives.

A semiconductor device fabrication method includes forming a substrate having first and second regions therein, with different densities of active regions in the first and second regions. A cell trench is formed, which defines cell active regions in the first region, and a peripheral trench is formed, which defines peripheral active regions in the second region. A first insulating layer is formed in the cell trench and the peripheral trench. A mask is selectively formed, which covers the first insulating layer in the first region and exposes the first insulating layer in the second region. A second insulating layer is formed on the first insulating layer in the second region exposed by the mask, using a selective dielectric-on-dielectric deposition process. The first insulating layer is exposed in the first region by removing the mask. A third insulating layer is formed on the first insulating layer in the first region and on the second insulating layer in the second region.

A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the hard mask layer with a set of parallel material lines delimiting gaps therebetween; and (c) providing a spacer layer following the shape of the material layer. The method further includes (d) removing a top portion of the spacer layer, thereby forming spacer lines alternatively separated by material lines and by gaps; and (e) providing a blocking element in a portion of a gap. The method also includes (f) etching selectively the hard mask layer by using the material layer, the spacer lines and the blocking element as a mask, thereby providing a first set of parallel trenches in the hardmask layer, wherein a trench has a blocked portion; and (g) selectively removing the blocking element.

The present disclosure provides a semiconductor device and a manufacturing method therefor. The device may include: a semiconductor substrate; a fin projecting from the semiconductor substrate, where trenches are formed on sides of the fin; a first insulator layer partially filling the trenches, where the fin protrudes from the first insulator layer; a second insulator layer covering the fin; a plurality of pseudo gate structures on the second insulator layer, where each pseudo gate structure wraps a part of the fin, where each pseudo gate structure includes a pseudo gate located on the second insulator layer, the plurality of pseudo gate structures includes at least a first pseudo gate structure and a second pseudo gate structure that are spaced from each other, the second pseudo gate structure is located at an edge corner of the fin, and a part of the second pseudo gate structure is on the first insulator layer; spacers, on the first insulator layer and the second insulator layer, at two sides of each of the plurality of pseudo gate structures; and a source or a drain located among the plurality of pseudo gate structures. The present invention can improve reliability of the device.

Examples of the disclosure relate to a sequential infiltration synthesis apparatus comprising: a reaction chamber constructed and arranged to accommodate at least one substrate; a first precursor flow path to provide the first precursor to the reaction chamber when a first flow controller is activated; a second precursor flow path to provide a second precursor to the reaction chamber when a second flow controller is activated; a removal flow path to allow removal of gas from the reaction chamber; a removal flow controller to create a gas flow in the reaction chamber to the removal flow path when the removal flow controller is activated; and, a sequence controller operably connected to the first, second and removal flow controllers and the sequence controller being programmed to enable infiltration of an infiltrateable material provided on the substrate in the reaction chamber. The apparatus may be provided with a heating system.

Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a film stack with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked semiconductor devices. In one embodiment, a method of forming a hardmask layer on a substrate includes forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in a processing chamber, forming a transition layer comprising born and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber, and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber.

A first film having a repetitive line pattern is formed on an under film. A second film is formed on a side surface of the first film. The second film has an etching selectivity different from that of the first film. A third film is formed on an upper surface and a side surface of the second film. The third film has an etching selectivity different from those of the first and second films. A resist pattern with an opening is formed on the third film. A recess that exposes upper surfaces of the first, second and third films is formed by etching the third film by using the resist pattern as an etching mask. An upper surface of the under film is exposed by etching the first and third films. A through hole that penetrates through the under film is formed by etching the under film.

Methods for forming a SiBN film comprising depositing a film on a feature on a substrate. The method comprises in a first cycle, depositing a SiB layer on a substrate in a chamber using a chemical vapor deposition process, the substrate having at least one feature thereon, the at least one feature comprising an upper surface, a bottom surface and sidewalls, the SiB layer formed on the upper surface, the bottom surface and the sidewalls. In a second cycle, the SiB layer is treated with a plasma comprising a nitrogen-containing gas to form a conformal SiBN film.